1 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
2 # This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
6 """LiteDRAM Controller."""
9 from nmigen
.utils
import log2_int
11 from gram
.common
import *
12 from gram
.phy
import dfi
13 from gram
.core
.refresher
import Refresher
14 from gram
.core
.bankmachine
import BankMachine
15 from gram
.core
.multiplexer
import Multiplexer
17 # Settings -----------------------------------------------------------------------------------------
18 __ALL__
= ["gramController"]
20 class ControllerSettings(Settings
):
24 cmd_buffer_buffered
=False,
32 refresh_cls
=Refresher
,
33 refresh_zqcs_freq
=1e0
,
37 with_auto_precharge
=True,
40 address_mapping
="ROW_BANK_COL"):
41 self
.set_attributes(locals())
43 # Controller ---------------------------------------------------------------------------------------
46 class gramController(Elaboratable
):
47 def __init__(self
, phy_settings
, geom_settings
, timing_settings
, clk_freq
,
48 controller_settings
=ControllerSettings()):
49 self
._address
_align
= log2_int(burst_lengths
[phy_settings
.memtype
])
51 # Settings ---------------------------------------------------------------------------------
52 self
.settings
= controller_settings
53 self
.settings
.phy
= phy_settings
54 self
.settings
.geom
= geom_settings
55 self
.settings
.timing
= timing_settings
57 # LiteDRAM Interface (User) ----------------------------------------------------------------
58 self
.interface
= interface
= gramInterface(
59 self
._address
_align
, self
.settings
)
61 # DFI Interface (Memory) -------------------------------------------------------------------
62 self
.dfi
= dfi
.Interface(
63 addressbits
=geom_settings
.addressbits
,
64 bankbits
=geom_settings
.bankbits
,
65 nranks
=phy_settings
.nranks
,
66 databits
=phy_settings
.dfi_databits
,
67 nphases
=phy_settings
.nphases
)
69 self
._clk
_freq
= clk_freq
71 def elaborate(self
, platform
):
74 nranks
= self
.settings
.phy
.nranks
75 nbanks
= 2**self
.settings
.geom
.bankbits
77 # Refresher --------------------------------------------------------------------------------
78 m
.submodules
.refresher
= Refresher(self
.settings
,
79 clk_freq
=self
._clk
_freq
,
80 zqcs_freq
=self
.settings
.refresh_zqcs_freq
,
81 postponing
=self
.settings
.refresh_postponing
)
83 # Bank Machines ----------------------------------------------------------------------------
85 for n
in range(nranks
*nbanks
):
86 bank_machine
= BankMachine(n
,
87 address_width
=self
.interface
.address_width
,
88 address_align
=self
._address
_align
,
90 settings
=self
.settings
)
91 bank_machines
.append(bank_machine
)
92 m
.submodules
+= bank_machine
93 m
.d
.comb
+= getattr(self
.interface
, "bank" +
94 str(n
)).connect(bank_machine
.req
)
96 # Multiplexer ------------------------------------------------------------------------------
97 m
.submodules
.multiplexer
= Multiplexer(
98 settings
=self
.settings
,
99 bank_machines
=bank_machines
,
100 refresher
=m
.submodules
.refresher
,
102 interface
=self
.interface
)