1 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
2 # This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
6 """LiteDRAM Controller."""
10 from gram
.common
import *
11 from gram
.phy
import dfi
12 from gram
.core
.refresher
import Refresher
13 from gram
.core
.bankmachine
import BankMachine
14 from gram
.core
.multiplexer
import Multiplexer
16 # Settings -----------------------------------------------------------------------------------------
18 class ControllerSettings(Settings
):
22 cmd_buffer_buffered
= False,
29 with_bandwidth
= False,
33 refresh_cls
= Refresher
,
34 refresh_zqcs_freq
= 1e0
,
35 refresh_postponing
= 1,
38 with_auto_precharge
= True,
41 address_mapping
= "ROW_BANK_COL"):
42 self
.set_attributes(locals())
44 # Controller ---------------------------------------------------------------------------------------
46 class gramController(Elaboratable
):
47 def __init__(self
, phy_settings
, geom_settings
, timing_settings
, clk_freq
,
48 controller_settings
=ControllerSettings()):
49 address_align
= log2_int(burst_lengths
[phy_settings
.memtype
])
51 # Settings ---------------------------------------------------------------------------------
52 self
.settings
= controller_settings
53 self
.settings
.phy
= phy_settings
54 self
.settings
.geom
= geom_settings
55 self
.settings
.timing
= timing_settings
57 nranks
= phy_settings
.nranks
58 nbanks
= 2**geom_settings
.bankbits
60 # LiteDRAM Interface (User) ----------------------------------------------------------------
61 self
.interface
= interface
= LiteDRAMInterface(address_align
, self
.settings
)
63 # DFI Interface (Memory) -------------------------------------------------------------------
64 self
.dfi
= dfi
.Interface(
65 addressbits
= geom_settings
.addressbits
,
66 bankbits
= geom_settings
.bankbits
,
67 nranks
= phy_settings
.nranks
,
68 databits
= phy_settings
.dfi_databits
,
69 nphases
= phy_settings
.nphases
)
71 def elaborate(self
, platform
):
74 # Refresher --------------------------------------------------------------------------------
75 m
.submodules
.refresher
= self
.settings
.refresh_cls(self
.settings
,
77 zqcs_freq
= self
.settings
.refresh_zqcs_freq
,
78 postponing
= self
.settings
.refresh_postponing
)
80 # Bank Machines ----------------------------------------------------------------------------
82 for n
in range(nranks
*nbanks
):
83 bank_machine
= BankMachine(n
,
84 address_width
= interface
.address_width
,
85 address_align
= address_align
,
87 settings
= self
.settings
)
88 bank_machines
.append(bank_machine
)
89 m
.submodules
+= bank_machine
90 m
.d
.comb
+= getattr(interface
, "bank"+str(n
)).connect(bank_machine
.req
)
92 # Multiplexer ------------------------------------------------------------------------------
93 m
.submodules
.multiplexer
= Multiplexer(
94 settings
= self
.settings
,
95 bank_machines
= bank_machines
,
96 refresher
= self
.refresher
,
98 interface
= interface
)
103 return self
.multiplexer
.get_csrs()