gram/core/controller.py

   1 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
   2 # This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   4 # License: BSD
   5
   6 """LiteDRAM Controller."""
   7
   8 from nmigen import *
   9 from nmigen.utils import log2_int
  10
  11 from gram.common import *
  12 from gram.phy import dfi
  13 from gram.core.refresher import Refresher
  14 from gram.core.bankmachine import BankMachine
  15 from gram.core.multiplexer import Multiplexer
  16
  17 # Settings -----------------------------------------------------------------------------------------
  18
  19 class ControllerSettings(Settings):
  20     def __init__(self,
  21         # Command buffers
  22         cmd_buffer_depth    = 8,
  23         cmd_buffer_buffered = False,
  24
  25         # Read/Write times
  26         read_time           = 32,
  27         write_time          = 16,
  28
  29         # Refresh
  30         with_refresh        = True,
  31         refresh_cls         = Refresher,
  32         refresh_zqcs_freq   = 1e0,
  33         refresh_postponing  = 1,
  34
  35         # Auto-Precharge
  36         with_auto_precharge = True,
  37
  38         # Address mapping
  39         address_mapping     = "ROW_BANK_COL"):
  40         self.set_attributes(locals())
  41
  42 # Controller ---------------------------------------------------------------------------------------
  43
  44 class gramController(Elaboratable):
  45     def __init__(self, phy_settings, geom_settings, timing_settings, clk_freq,
  46         controller_settings=ControllerSettings()):
  47         self._address_align = log2_int(burst_lengths[phy_settings.memtype])
  48
  49         # Settings ---------------------------------------------------------------------------------
  50         self.settings        = controller_settings
  51         self.settings.phy    = phy_settings
  52         self.settings.geom   = geom_settings
  53         self.settings.timing = timing_settings
  54
  55         # LiteDRAM Interface (User) ----------------------------------------------------------------
  56         self.interface = interface = gramInterface(self._address_align, self.settings)
  57
  58         # DFI Interface (Memory) -------------------------------------------------------------------
  59         self.dfi = dfi.Interface(
  60             addressbits = geom_settings.addressbits,
  61             bankbits    = geom_settings.bankbits,
  62             nranks      = phy_settings.nranks,
  63             databits    = phy_settings.dfi_databits,
  64             nphases     = phy_settings.nphases)
  65
  66         self._clk_freq = clk_freq
  67
  68     def elaborate(self, platform):
  69         m = Module()
  70
  71         nranks = self.settings.phy.nranks
  72         nbanks = 2**self.settings.geom.bankbits
  73
  74         # Refresher --------------------------------------------------------------------------------
  75         m.submodules.refresher = self.settings.refresh_cls(self.settings,
  76             clk_freq   = self._clk_freq,
  77             zqcs_freq  = self.settings.refresh_zqcs_freq,
  78             postponing = self.settings.refresh_postponing)
  79
  80         # Bank Machines ----------------------------------------------------------------------------
  81         bank_machines = []
  82         for n in range(nranks*nbanks):
  83             bank_machine = BankMachine(n,
  84                 address_width = self.interface.address_width,
  85                 address_align = self._address_align,
  86                 nranks        = nranks,
  87                 settings      = self.settings)
  88             bank_machines.append(bank_machine)
  89             m.submodules += bank_machine
  90             m.d.comb += getattr(self.interface, "bank"+str(n)).connect(bank_machine.req)
  91
  92         # Multiplexer ------------------------------------------------------------------------------
  93         m.submodules.multiplexer = Multiplexer(
  94             settings      = self.settings,
  95             bank_machines = bank_machines,
  96             refresher     = m.submodules.refresher,
  97             dfi           = self.dfi,
  98             interface     = self.interface)
  99
 100         return m
 101
 102     def get_csrs(self):
 103         return self.multiplexer.get_csrs()