Connect dramcore to SoC bus in ECPIX-5 example
[gram.git] / gram / dfii.py
1 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
2 # This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
4 # License: BSD
5
6 from nmigen import *
7
8 from gram.phy import dfi
9 from gram.compat import CSRPrefixProxy
10 from lambdasoc.periph import Peripheral
11
12 # PhaseInjector ------------------------------------------------------------------------------------
13
14 class PhaseInjector(Elaboratable):
15 def __init__(self, csr_bank, phase):
16 self._command = csr_bank.csr(6, "rw")
17 self._command_issue = csr_bank.csr(1, "rw")
18 self._address = csr_bank.csr(len(phase.address), "rw")
19 self._baddress = csr_bank.csr(len(phase.bank), "rw")
20 self._wrdata = csr_bank.csr(len(phase.wrdata), "rw")
21 self._rddata = csr_bank.csr(len(phase.rddata), "rw")
22
23 self._phase = phase
24
25 def elaborate(self, platform):
26 m = Module()
27
28 m.d.comb += [
29 self._phase.address.eq(self._address.r_data),
30 self._phase.bank.eq(self._baddress.r_data),
31 self._phase.wrdata_en.eq(self._command_issue.r_stb & self._command.r_data[4]),
32 self._phase.rddata_en.eq(self._command_issue.r_stb & self._command.r_data[5]),
33 self._phase.wrdata.eq(self._wrdata.r_data),
34 self._phase.wrdata_mask.eq(0)
35 ]
36
37 with m.If(self._command_issue.r_stb):
38 m.d.comb += [
39 self._phase.cs_n.eq(Repl(value=~self._command.r_data[0], count=len(self._phase.cs_n))),
40 self._phase.we_n.eq(~self._command.r_data[1]),
41 self._phase.cas_n.eq(~self._command.r_data[2]),
42 self._phase.ras_n.eq(~self._command.r_data[3]),
43 ]
44 with m.Else():
45 m.d.comb += [
46 self._phase.cs_n.eq(Repl(value=1, count=len(self._phase.cs_n))),
47 self._phase.we_n.eq(1),
48 self._phase.cas_n.eq(1),
49 self._phase.ras_n.eq(1),
50 ]
51
52 with m.If(self._phase.rddata_valid):
53 m.d.sync += self._rddata.w_data.eq(self._phase.rddata)
54
55 return m
56
57 # DFIInjector --------------------------------------------------------------------------------------
58
59 class DFIInjector(Elaboratable):
60 def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
61 self._nranks = nranks
62
63 self._inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
64 self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
65 self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
66
67 self._control = csr_bank.csr(4, "rw") # sel, cke, odt, reset_n
68
69 self._phases = []
70 for n, phase in enumerate(self._inti.phases):
71 self._phases += [PhaseInjector(CSRPrefixProxy(csr_bank, "p{}".format(n)), phase)]
72
73 def elaborate(self, platform):
74 m = Module()
75
76 m.submodules += self._phases
77
78 with m.If(self._control.r_data[0]):
79 m.d.comb += self.slave.connect(self.master)
80 with m.Else():
81 m.d.comb += self._inti.connect(self.master)
82
83 for i in range(self._nranks):
84 m.d.comb += [phase.cke[i].eq(self._control.r_data[1]) for phase in self._inti.phases]
85 m.d.comb += [phase.odt[i].eq(self._control.r_data[2]) for phase in self._inti.phases if hasattr(phase, "odt")]
86 m.d.comb += [phase.reset_n.eq(self._control.r_data[3]) for phase in self._inti.phases if hasattr(phase, "reset_n")]
87
88 return m