1 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
2 # This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
8 from gram
.phy
import dfi
9 from gram
.compat
import CSRPrefixProxy
11 # PhaseInjector ------------------------------------------------------------------------------------
14 class PhaseInjector(Elaboratable
):
15 def __init__(self
, csr_bank
, phase
):
16 self
._command
= csr_bank
.csr(6, "rw")
17 self
._command
_issue
= csr_bank
.csr(1, "rw")
18 self
._address
= csr_bank
.csr(len(phase
.address
), "rw")
19 self
._baddress
= csr_bank
.csr(len(phase
.bank
), "rw")
20 self
._wrdata
= csr_bank
.csr(len(phase
.wrdata
), "rw")
21 self
._rddata
= csr_bank
.csr(len(phase
.rddata
), "rw")
25 def elaborate(self
, platform
):
29 self
._phase
.address
.eq(self
._address
.r_data
),
30 self
._phase
.bank
.eq(self
._baddress
.r_data
),
31 self
._phase
.wrdata_en
.eq(
32 self
._command
_issue
.r_stb
& self
._command
.r_data
[4]),
33 self
._phase
.rddata_en
.eq(
34 self
._command
_issue
.r_stb
& self
._command
.r_data
[5]),
35 self
._phase
.wrdata
.eq(self
._wrdata
.r_data
),
36 self
._phase
.wrdata_mask
.eq(0)
39 with m
.If(self
._command
_issue
.r_stb
):
42 Repl(value
=~self
._command
.r_data
[0], count
=len(self
._phase
.cs_n
))),
43 self
._phase
.we_n
.eq(~self
._command
.r_data
[1]),
44 self
._phase
.cas_n
.eq(~self
._command
.r_data
[2]),
45 self
._phase
.ras_n
.eq(~self
._command
.r_data
[3]),
50 Repl(value
=1, count
=len(self
._phase
.cs_n
))),
51 self
._phase
.we_n
.eq(1),
52 self
._phase
.cas_n
.eq(1),
53 self
._phase
.ras_n
.eq(1),
56 with m
.If(self
._phase
.rddata_valid
):
57 m
.d
.sync
+= self
._rddata
.r_data
.eq(self
._phase
.rddata
)
61 # DFIInjector --------------------------------------------------------------------------------------
64 class DFIInjector(Elaboratable
):
65 def __init__(self
, csr_bank
, addressbits
, bankbits
, nranks
, databits
, nphases
=1):
68 self
._inti
= dfi
.Interface(
69 addressbits
, bankbits
, nranks
, databits
, nphases
)
70 self
.slave
= dfi
.Interface(
71 addressbits
, bankbits
, nranks
, databits
, nphases
)
72 self
.master
= dfi
.Interface(
73 addressbits
, bankbits
, nranks
, databits
, nphases
)
75 self
._control
= csr_bank
.csr(4, "rw") # sel, cke, odt, reset_n
78 for n
, phase
in enumerate(self
._inti
.phases
):
79 self
._phases
+= [PhaseInjector(CSRPrefixProxy(csr_bank
,
80 "p{}".format(n
)), phase
)]
82 def elaborate(self
, platform
):
85 m
.submodules
+= self
._phases
87 with m
.If(self
._control
.r_data
[0]):
88 m
.d
.comb
+= self
.slave
.connect(self
.master
)
90 m
.d
.comb
+= self
._inti
.connect(self
.master
)
92 for i
in range(self
._nranks
):
93 m
.d
.comb
+= [phase
.cke
[i
].eq(self
._control
.r_data
[1])
94 for phase
in self
._inti
.phases
]
95 m
.d
.comb
+= [phase
.odt
[i
].eq(self
._control
.r_data
[2])
96 for phase
in self
._inti
.phases
if hasattr(phase
, "odt")]
97 m
.d
.comb
+= [phase
.reset_n
.eq(self
._control
.r_data
[3])
98 for phase
in self
._inti
.phases
if hasattr(phase
, "reset_n")]