gram/gen.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # This file is Copyright (c) 2020 Stefan Schrijvers <ximin@ximinity.net>
   5 # License: BSD
   6
   7 """
   8 LiteDRAM standalone core generator
   9
  10 LiteDRAM aims to be directly used as a python package when the SoC is created using LiteX. However,
  11 for some use cases it could be interesting to generate a standalone verilog file of the core:
  12 - integration of the core in a SoC using a more traditional flow.
  13 - need to version/package the core.
  14 - avoid Migen/LiteX dependencies.
  15 - etc...
  16
  17 The standalone core is generated from a YAML configuration file that allows the user to generate
  18 easily a custom configuration of the core.
  19
  20 Current version of the generator is limited to DDR2/DDR3 Xilinx 7-Series FPGA and DDR3 on Lattice
  21 ECP5.
  22 """
  23
  24 import os
  25 import sys
  26 import math
  27 import struct
  28 import yaml
  29 import argparse
  30
  31 from migen import *
  32 from migen.genlib.resetsync import AsyncResetSynchronizer
  33
  34 from litex.build.tools import replace_in_file
  35 from litex.build.generic_platform import *
  36 from litex.build.xilinx import XilinxPlatform
  37 from litex.build.lattice import LatticePlatform
  38 from litex.boards.platforms import versa_ecp5
  39
  40 from litex.soc.cores.clock import *
  41 from litex.soc.integration.soc_core import *
  42 from litex.soc.integration.builder import *
  43 from litex.soc.interconnect import wishbone
  44 from litex.soc.cores.uart import *
  45
  46 from gram import modules as litedram_modules
  47 from gram import phy as litedram_phys
  48 from gram.phy.ecp5ddrphy import ECP5DDRPHY
  49 from gram.phy.s7ddrphy import S7DDRPHY
  50 from gram.core.controller import ControllerSettings
  51 from gram.frontend.axi import *
  52 from gram.frontend.wishbone import *
  53 from gram.frontend.bist import LiteDRAMBISTGenerator
  54 from gram.frontend.bist import LiteDRAMBISTChecker
  55 from gram.frontend.fifo import LiteDRAMFIFO
  56
  57 # IOs/Interfaces -----------------------------------------------------------------------------------
  58
  59 def get_common_ios():
  60     return [
  61         # clk / rst
  62         ("clk", 0, Pins(1)),
  63         ("rst", 0, Pins(1)),
  64
  65         # serial
  66         ("serial", 0,
  67             Subsignal("tx", Pins(1)),
  68             Subsignal("rx", Pins(1))
  69         ),
  70
  71         # crg status
  72         ("pll_locked", 0, Pins(1)),
  73
  74         # init status
  75         ("init_done",  0, Pins(1)),
  76         ("init_error", 0, Pins(1)),
  77
  78         # iodelay clk / rst
  79         ("clk_iodelay", 0, Pins(1)),
  80         ("rst_iodelay", 0, Pins(1)),
  81
  82         # user clk / rst
  83         ("user_clk", 0, Pins(1)),
  84         ("user_rst", 0, Pins(1))
  85     ]
  86
  87 def get_dram_ios(core_config):
  88     sdram_module = core_config["sdram_module"]
  89     return [
  90         ("ddram", 0,
  91             Subsignal("a",       Pins(log2_int(core_config["sdram_module"].nrows))),
  92             Subsignal("ba",      Pins(log2_int(core_config["sdram_module"].nbanks))),
  93             Subsignal("ras_n",   Pins(1)),
  94             Subsignal("cas_n",   Pins(1)),
  95             Subsignal("we_n",    Pins(1)),
  96             Subsignal("cs_n",    Pins(core_config["sdram_rank_nb"])),
  97             Subsignal("dm",      Pins(core_config["sdram_module_nb"])),
  98             Subsignal("dq",      Pins(8*core_config["sdram_module_nb"])),
  99             Subsignal("dqs_p",   Pins(core_config["sdram_module_nb"])),
 100             Subsignal("dqs_n",   Pins(core_config["sdram_module_nb"])),
 101             Subsignal("clk_p",   Pins(core_config["sdram_rank_nb"])),
 102             Subsignal("clk_n",   Pins(core_config["sdram_rank_nb"])),
 103             Subsignal("cke",     Pins(core_config["sdram_rank_nb"])),
 104             Subsignal("odt",     Pins(core_config["sdram_rank_nb"])),
 105             Subsignal("reset_n", Pins(1))
 106         ),
 107     ]
 108
 109 def get_native_user_port_ios(_id, aw, dw):
 110     return [
 111         ("user_port_{}".format(_id), 0,
 112             # cmd
 113             Subsignal("cmd_valid", Pins(1)),
 114             Subsignal("cmd_ready", Pins(1)),
 115             Subsignal("cmd_we",    Pins(1)),
 116             Subsignal("cmd_addr",  Pins(aw)),
 117
 118             # wdata
 119             Subsignal("wdata_valid", Pins(1)),
 120             Subsignal("wdata_ready", Pins(1)),
 121             Subsignal("wdata_we",    Pins(dw//8)),
 122             Subsignal("wdata_data",  Pins(dw)),
 123
 124             # rdata
 125             Subsignal("rdata_valid", Pins(1)),
 126             Subsignal("rdata_ready", Pins(1)),
 127             Subsignal("rdata_data",  Pins(dw))
 128         ),
 129     ]
 130
 131 def get_wishbone_user_port_ios(_id, aw, dw):
 132     return [
 133         ("user_port_{}".format(_id), 0,
 134             Subsignal("adr",   Pins(aw)),
 135             Subsignal("dat_w", Pins(dw)),
 136             Subsignal("dat_r", Pins(dw)),
 137             Subsignal("sel",   Pins(dw//8)),
 138             Subsignal("cyc",   Pins(1)),
 139             Subsignal("stb",   Pins(1)),
 140             Subsignal("ack",   Pins(1)),
 141             Subsignal("we",    Pins(1)),
 142             Subsignal("err",   Pins(1)),
 143         ),
 144     ]
 145
 146 def get_axi_user_port_ios(_id, aw, dw, iw):
 147     return [
 148         ("user_port_{}".format(_id), 0,
 149             # aw
 150             Subsignal("awvalid", Pins(1)),
 151             Subsignal("awready", Pins(1)),
 152             Subsignal("awaddr",  Pins(aw)),
 153             Subsignal("awburst", Pins(2)),
 154             Subsignal("awlen",   Pins(8)),
 155             Subsignal("awsize",  Pins(4)),
 156             Subsignal("awid",    Pins(iw)),
 157
 158             # w
 159             Subsignal("wvalid", Pins(1)),
 160             Subsignal("wready", Pins(1)),
 161             Subsignal("wlast",  Pins(1)),
 162             Subsignal("wstrb",  Pins(dw//8)),
 163             Subsignal("wdata",  Pins(dw)),
 164
 165             # b
 166             Subsignal("bvalid", Pins(1)),
 167             Subsignal("bready", Pins(1)),
 168             Subsignal("bresp",  Pins(2)),
 169             Subsignal("bid",    Pins(iw)),
 170
 171             # ar
 172             Subsignal("arvalid", Pins(1)),
 173             Subsignal("arready", Pins(1)),
 174             Subsignal("araddr",  Pins(aw)),
 175             Subsignal("arburst", Pins(2)),
 176             Subsignal("arlen",   Pins(8)),
 177             Subsignal("arsize",  Pins(4)),
 178             Subsignal("arid",    Pins(iw)),
 179
 180             # r
 181             Subsignal("rvalid", Pins(1)),
 182             Subsignal("rready", Pins(1)),
 183             Subsignal("rlast",  Pins(1)),
 184             Subsignal("rresp",  Pins(2)),
 185             Subsignal("rdata",  Pins(dw)),
 186             Subsignal("rid",    Pins(iw))
 187         ),
 188     ]
 189
 190 def get_fifo_user_port_ios(_id, dw):
 191     return [
 192         ("user_fifo_{}".format(_id), 0,
 193             # in
 194             Subsignal("in_valid", Pins(1)),
 195             Subsignal("in_ready", Pins(1)),
 196             Subsignal("in_data",  Pins(dw)),
 197
 198             # out
 199             Subsignal("out_valid", Pins(1)),
 200             Subsignal("out_ready", Pins(1)),
 201             Subsignal("out_data",  Pins(dw)),
 202         ),
 203     ]
 204
 205
 206 class Platform(XilinxPlatform):
 207     def __init__(self):
 208         XilinxPlatform.__init__(self, "", io=[], toolchain="vivado")
 209
 210 # CRG ----------------------------------------------------------------------------------------------
 211
 212 class LiteDRAMECP5DDRPHYCRG(Module):
 213     def __init__(self, platform, core_config):
 214         self.clock_domains.cd_init    = ClockDomain()
 215         self.clock_domains.cd_por     = ClockDomain(reset_less=True)
 216         self.clock_domains.cd_sys     = ClockDomain()
 217         self.clock_domains.cd_sys2x   = ClockDomain()
 218         self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
 219
 220         # # #
 221
 222         self.stop = Signal()
 223
 224         # clk / rst
 225         clk = platform.request("clk")
 226         rst = platform.request("rst")
 227
 228         # power on reset
 229         por_count = Signal(16, reset=2**16-1)
 230         por_done  = Signal()
 231         self.comb += self.cd_por.clk.eq(ClockSignal())
 232         self.comb += por_done.eq(por_count == 0)
 233         self.sync.por += If(~por_done, por_count.eq(por_count - 1))
 234
 235         # pll
 236         self.submodules.pll = pll = ECP5PLL()
 237         pll.register_clkin(clk, core_config["input_clk_freq"])
 238         pll.create_clkout(self.cd_sys2x_i, 2*core_config["sys_clk_freq"])
 239         pll.create_clkout(self.cd_init, core_config["init_clk_freq"])
 240         self.specials += [
 241             Instance("ECLKSYNCB",
 242                 i_ECLKI = self.cd_sys2x_i.clk,
 243                 i_STOP  = self.stop,
 244                 o_ECLKO = self.cd_sys2x.clk),
 245             Instance("CLKDIVF",
 246                 p_DIV     = "2.0",
 247                 i_ALIGNWD = 0,
 248                 i_CLKI    = self.cd_sys2x.clk,
 249                 i_RST     = self.cd_sys2x.rst,
 250                 o_CDIVX   = self.cd_sys.clk),
 251             AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst),
 252             AsyncResetSynchronizer(self.cd_sys,  ~por_done | ~pll.locked | rst),
 253         ]
 254
 255 class LiteDRAMS7DDRPHYCRG(Module):
 256     def __init__(self, platform, core_config):
 257         self.clock_domains.cd_sys = ClockDomain()
 258         if core_config["memtype"] == "DDR3":
 259             self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
 260             self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
 261         else:
 262             self.clock_domains.cd_sys2x     = ClockDomain(reset_less=True)
 263             self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
 264         self.clock_domains.cd_iodelay = ClockDomain()
 265
 266         # # #
 267
 268         clk = platform.request("clk")
 269         rst = platform.request("rst")
 270
 271         self.submodules.sys_pll = sys_pll = S7PLL(speedgrade=core_config["speedgrade"])
 272         self.comb += sys_pll.reset.eq(rst)
 273         sys_pll.register_clkin(clk, core_config["input_clk_freq"])
 274         sys_pll.create_clkout(self.cd_sys, core_config["sys_clk_freq"])
 275         if core_config["memtype"] == "DDR3":
 276             sys_pll.create_clkout(self.cd_sys4x, 4*core_config["sys_clk_freq"])
 277             sys_pll.create_clkout(self.cd_sys4x_dqs, 4*core_config["sys_clk_freq"], phase=90)
 278         else:
 279             sys_pll.create_clkout(self.cd_sys2x, 2*core_config["sys_clk_freq"])
 280             sys_pll.create_clkout(self.cd_sys2x_dqs, 2*core_config["sys_clk_freq"], phase=90)
 281         self.comb += platform.request("pll_locked").eq(sys_pll.locked)
 282
 283         self.submodules.iodelay_pll = iodelay_pll = S7PLL(speedgrade=core_config["speedgrade"])
 284         self.comb += iodelay_pll.reset.eq(rst)
 285         iodelay_pll.register_clkin(clk, core_config["input_clk_freq"])
 286         iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
 287         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay)
 288
 289 # LiteDRAMCoreControl ------------------------------------------------------------------------------
 290
 291 class LiteDRAMCoreControl(Module, AutoCSR):
 292     def __init__(self):
 293         self.init_done  = CSRStorage()
 294         self.init_error = CSRStorage()
 295
 296 # LiteDRAMCore -------------------------------------------------------------------------------------
 297
 298 class LiteDRAMCore(SoCCore):
 299     def __init__(self, platform, core_config, **kwargs):
 300         platform.add_extension(get_common_ios())
 301
 302         # Parameters -------------------------------------------------------------------------------
 303         sys_clk_freq  = core_config["sys_clk_freq"]
 304         cpu_type      = core_config["cpu"]
 305         cpu_variant   = core_config.get("cpu_variant", "standard")
 306         csr_alignment = core_config.get("csr_alignment", 32)
 307         if cpu_type is None:
 308             kwargs["integrated_rom_size"]  = 0
 309             kwargs["integrated_sram_size"] = 0
 310             kwargs["with_uart"]            = False
 311             kwargs["with_timer"]           = False
 312             kwargs["with_ctrl"]            = False
 313
 314         # SoCCore ----------------------------------------------------------------------------------
 315         SoCCore.__init__(self, platform, sys_clk_freq,
 316             cpu_type      = cpu_type,
 317             cpu_variant   = cpu_variant,
 318             csr_alignment = csr_alignment,
 319             **kwargs)
 320
 321         # CRG --------------------------------------------------------------------------------------
 322         if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
 323             self.submodules.crg = crg = LiteDRAMECP5DDRPHYCRG(platform, core_config)
 324         if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
 325             self.submodules.crg = LiteDRAMS7DDRPHYCRG(platform, core_config)
 326
 327         # DRAM -------------------------------------------------------------------------------------
 328         platform.add_extension(get_dram_ios(core_config))
 329         # ECP5DDRPHY
 330         if core_config["sdram_phy"] in  [litedram_phys.ECP5DDRPHY]:
 331             assert core_config["memtype"] in ["DDR3"]
 332             self.submodules.ddrphy = core_config["sdram_phy"](
 333                 pads         = platform.request("ddram"),
 334                 sys_clk_freq = sys_clk_freq)
 335             self.comb += crg.stop.eq(self.ddrphy.init.stop)
 336             self.add_constant("ECP5DDRPHY")
 337             sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
 338         # S7DDRPHY
 339         if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
 340             assert core_config["memtype"] in ["DDR2", "DDR3"]
 341             self.submodules.ddrphy = core_config["sdram_phy"](
 342                 pads             = platform.request("ddram"),
 343                 memtype          = core_config["memtype"],
 344                 nphases          = 4 if core_config["memtype"] == "DDR3" else 2,
 345                 sys_clk_freq     = sys_clk_freq,
 346                 iodelay_clk_freq = core_config["iodelay_clk_freq"],
 347                 cmd_latency      = core_config["cmd_latency"])
 348             self.add_constant("CMD_DELAY", core_config["cmd_delay"])
 349             if core_config["memtype"] == "DDR3":
 350                 self.ddrphy.settings.add_electrical_settings(
 351                     rtt_nom = core_config["rtt_nom"],
 352                     rtt_wr  = core_config["rtt_wr"],
 353                     ron     = core_config["ron"])
 354         self.add_csr("ddrphy")
 355
 356         sdram_module = core_config["sdram_module"](sys_clk_freq,
 357             "1:4" if core_config["memtype"] == "DDR3" else "1:2")
 358         controller_settings = controller_settings = ControllerSettings(
 359             cmd_buffer_depth=core_config["cmd_buffer_depth"])
 360         self.add_sdram("sdram",
 361             phy                     = self.ddrphy,
 362             module                  = sdram_module,
 363             origin                  = self.mem_map["main_ram"],
 364             size                    = 0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib.
 365             with_soc_interconnect   = cpu_type is not None,
 366             l2_cache_size           = 0,
 367             l2_cache_min_data_width = 0,
 368             controller_settings     = controller_settings,
 369         )
 370
 371         # DRAM Control/Status ----------------------------------------------------------------------
 372         # Expose calibration status to user.
 373         self.submodules.ddrctrl = LiteDRAMCoreControl()
 374         self.add_csr("ddrctrl")
 375         self.comb += platform.request("init_done").eq(self.ddrctrl.init_done.storage)
 376         self.comb += platform.request("init_error").eq(self.ddrctrl.init_error.storage)
 377         # If no CPU, expose a bus control interface to user.
 378         if cpu_type is None:
 379             wb_bus = wishbone.Interface()
 380             self.bus.add_master(master=wb_bus)
 381             platform.add_extension(wb_bus.get_ios("wb_ctrl"))
 382             wb_pads = platform.request("wb_ctrl")
 383             self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
 384
 385         # User ports -------------------------------------------------------------------------------
 386         self.comb += [
 387             platform.request("user_clk").eq(ClockSignal()),
 388             platform.request("user_rst").eq(ResetSignal())
 389         ]
 390         for name, port in core_config["user_ports"].items():
 391             # Native -------------------------------------------------------------------------------
 392             if port["type"] == "native":
 393                 user_port = self.sdram.crossbar.get_port()
 394                 platform.add_extension(get_native_user_port_ios(name,
 395                     user_port.address_width,
 396                     user_port.data_width))
 397                 _user_port_io = platform.request("user_port_{}".format(name))
 398                 self.comb += [
 399                     # cmd
 400                     user_port.cmd.valid.eq(_user_port_io.cmd_valid),
 401                     _user_port_io.cmd_ready.eq(user_port.cmd.ready),
 402                     user_port.cmd.we.eq(_user_port_io.cmd_we),
 403                     user_port.cmd.addr.eq(_user_port_io.cmd_addr),
 404
 405                     # wdata
 406                     user_port.wdata.valid.eq(_user_port_io.wdata_valid),
 407                     _user_port_io.wdata_ready.eq(user_port.wdata.ready),
 408                     user_port.wdata.we.eq(_user_port_io.wdata_we),
 409                     user_port.wdata.data.eq(_user_port_io.wdata_data),
 410
 411                     # rdata
 412                     _user_port_io.rdata_valid.eq(user_port.rdata.valid),
 413                     user_port.rdata.ready.eq(_user_port_io.rdata_ready),
 414                     _user_port_io.rdata_data.eq(user_port.rdata.data),
 415                 ]
 416             # Wishbone -----------------------------------------------------------------------------
 417             elif port["type"] == "wishbone":
 418                 user_port = self.sdram.crossbar.get_port()
 419                 wb_port = wishbone.Interface(
 420                     user_port.data_width,
 421                     user_port.address_width)
 422                 wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port)
 423                 self.submodules += wishbone2native
 424                 platform.add_extension(get_wishbone_user_port_ios(name,
 425                         len(wb_port.adr),
 426                         len(wb_port.dat_w)))
 427                 _wb_port_io = platform.request("user_port_{}".format(name))
 428                 self.comb += [
 429                     wb_port.adr.eq(_wb_port_io.adr),
 430                     wb_port.dat_w.eq(_wb_port_io.dat_w),
 431                     _wb_port_io.dat_r.eq(wb_port.dat_r),
 432                     wb_port.sel.eq(_wb_port_io.sel),
 433                     wb_port.cyc.eq(_wb_port_io.cyc),
 434                     wb_port.stb.eq(_wb_port_io.stb),
 435                     _wb_port_io.ack.eq(wb_port.ack),
 436                     wb_port.we.eq(_wb_port_io.we),
 437                     _wb_port_io.err.eq(wb_port.err),
 438                 ]
 439             # AXI ----------------------------------------------------------------------------------
 440             elif port["type"] == "axi":
 441                 user_port = self.sdram.crossbar.get_port()
 442                 axi_port  = LiteDRAMAXIPort(
 443                     user_port.data_width,
 444                     user_port.address_width + log2_int(user_port.data_width//8),
 445                     port["id_width"])
 446                 axi2native = LiteDRAMAXI2Native(axi_port, user_port)
 447                 self.submodules += axi2native
 448                 platform.add_extension(get_axi_user_port_ios(name,
 449                         axi_port.address_width,
 450                         axi_port.data_width,
 451                         port["id_width"]))
 452                 _axi_port_io = platform.request("user_port_{}".format(name))
 453                 self.comb += [
 454                     # aw
 455                     axi_port.aw.valid.eq(_axi_port_io.awvalid),
 456                     _axi_port_io.awready.eq(axi_port.aw.ready),
 457                     axi_port.aw.addr.eq(_axi_port_io.awaddr),
 458                     axi_port.aw.burst.eq(_axi_port_io.awburst),
 459                     axi_port.aw.len.eq(_axi_port_io.awlen),
 460                     axi_port.aw.size.eq(_axi_port_io.awsize),
 461                     axi_port.aw.id.eq(_axi_port_io.awid),
 462
 463                     # w
 464                     axi_port.w.valid.eq(_axi_port_io.wvalid),
 465                     _axi_port_io.wready.eq(axi_port.w.ready),
 466                     axi_port.w.last.eq(_axi_port_io.wlast),
 467                     axi_port.w.strb.eq(_axi_port_io.wstrb),
 468                     axi_port.w.data.eq(_axi_port_io.wdata),
 469
 470                     # b
 471                     _axi_port_io.bvalid.eq(axi_port.b.valid),
 472                     axi_port.b.ready.eq(_axi_port_io.bready),
 473                     _axi_port_io.bresp.eq(axi_port.b.resp),
 474                     _axi_port_io.bid.eq(axi_port.b.id),
 475
 476                     # ar
 477                     axi_port.ar.valid.eq(_axi_port_io.arvalid),
 478                     _axi_port_io.arready.eq(axi_port.ar.ready),
 479                     axi_port.ar.addr.eq(_axi_port_io.araddr),
 480                     axi_port.ar.burst.eq(_axi_port_io.arburst),
 481                     axi_port.ar.len.eq(_axi_port_io.arlen),
 482                     axi_port.ar.size.eq(_axi_port_io.arsize),
 483                     axi_port.ar.id.eq(_axi_port_io.arid),
 484
 485                     # r
 486                     _axi_port_io.rvalid.eq(axi_port.r.valid),
 487                     axi_port.r.ready.eq(_axi_port_io.rready),
 488                     _axi_port_io.rlast.eq(axi_port.r.last),
 489                     _axi_port_io.rresp.eq(axi_port.r.resp),
 490                     _axi_port_io.rdata.eq(axi_port.r.data),
 491                     _axi_port_io.rid.eq(axi_port.r.id),
 492                 ]
 493             # FIFO ---------------------------------------------------------------------------------
 494             elif port["type"] == "fifo":
 495                 platform.add_extension(get_fifo_user_port_ios(name, user_port.data_width))
 496                 _user_fifo_io = platform.request("user_fifo_{}".format(name))
 497                 fifo = LiteDRAMFIFO(
 498                     data_width      = user_port.data_width,
 499                     base            = port["base"],
 500                     depth           = port["depth"],
 501                     write_port      = self.sdram.crossbar.get_port("write"),
 502                     write_threshold = port["depth"] - 32, # FIXME
 503                     read_port       = self.sdram.crossbar.get_port("read"),
 504                     read_threshold  = 32 # FIXME
 505                 )
 506                 self.submodules += fifo
 507                 self.comb += [
 508                     # in
 509                     fifo.sink.valid.eq(_user_fifo_io.in_valid),
 510                     _user_fifo_io.in_ready.eq(fifo.sink.ready),
 511                     fifo.sink.data.eq(_user_fifo_io.in_data),
 512
 513                     # out
 514                     _user_fifo_io.out_valid.eq(fifo.source.valid),
 515                     fifo.source.ready.eq(_user_fifo_io.out_ready),
 516                     _user_fifo_io.out_data.eq(fifo.source.data),
 517                 ]
 518             else:
 519                 raise ValueError("Unsupported port type: {}".format(port["type"]))
 520
 521 # Build --------------------------------------------------------------------------------------------
 522
 523 def main():
 524     parser = argparse.ArgumentParser(description="LiteDRAM standalone core generator")
 525     builder_args(parser)
 526     parser.set_defaults(output_dir="build")
 527     parser.add_argument("config", help="YAML config file")
 528     args = parser.parse_args()
 529     core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
 530
 531     # Convert YAML elements to Python/LiteX --------------------------------------------------------
 532     for k, v in core_config.items():
 533         replaces = {"False": False, "True": True, "None": None}
 534         for r in replaces.keys():
 535             if v == r:
 536                 core_config[k] = replaces[r]
 537         if "clk_freq" in k:
 538             core_config[k] = float(core_config[k])
 539         if k == "sdram_module":
 540             core_config[k] = getattr(litedram_modules, core_config[k])
 541         if k == "sdram_phy":
 542             core_config[k] = getattr(litedram_phys, core_config[k])
 543
 544     # Generate core --------------------------------------------------------------------------------
 545     if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
 546         platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") # FIXME: allow other devices.
 547     elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
 548         platform = XilinxPlatform("", io=[], toolchain="vivado")
 549     else:
 550         raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"]))
 551
 552     builder_arguments = builder_argdict(args)
 553     builder_arguments["compile_gateware"] = False
 554
 555     soc      = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000)
 556     builder  = Builder(soc, **builder_arguments)
 557     vns      = builder.build(build_name="litedram_core", regular_comb=False)
 558
 559     if soc.cpu_type is not None:
 560         init_filename = "mem.init"
 561         os.system("mv {} {}".format(
 562             os.path.join(builder.gateware_dir, init_filename),
 563             os.path.join(builder.gateware_dir, "litedram_core.init"),
 564         ))
 565         replace_in_file(os.path.join(builder.gateware_dir, "litedram_core.v"), init_filename, "litedram_core.init")
 566
 567 if __name__ == "__main__":
 568     main()