1 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
2 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
3 # This file is Copyright (c) 2018 John Sully <john@csquare.ca>
4 # This file is Copyright (c) 2019 Ambroz Bizjak <abizjak.pro@gmail.com>
5 # This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
6 # This file is Copyright (c) 2018 bunnie <bunnie@kosagi.com>
7 # This file is Copyright (c) 2018 David Shah <dave@ds0.me>
8 # This file is Copyright (c) 2019 Steve Haynal - VSD Engineering
9 # This file is Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
10 # This file is Copyright (c) 2018 Daniel Kucera <daniel.kucera@gmail.com>
11 # This file is Copyright (c) 2018 Mikołaj Sowiński <mikolaj.sowinski@gmail.com>
12 # This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
16 from collections
import namedtuple
18 from nmigen
.utils
import log2_int
20 from gram
.common
import Settings
, GeomSettings
, TimingSettings
22 # Timings ------------------------------------------------------------------------------------------
24 _technology_timings
= ["tREFI", "tWTR", "tCCD", "tRRD", "tZQCS"]
26 class _TechnologyTimings(Settings
):
27 def __init__(self
, tREFI
, tWTR
, tCCD
, tRRD
, tZQCS
=None):
28 self
.set_attributes(locals())
31 _speedgrade_timings
= ["tRP", "tRCD", "tWR", "tRFC", "tFAW", "tRAS"]
33 class _SpeedgradeTimings(Settings
):
34 def __init__(self
, tRP
, tRCD
, tWR
, tRFC
, tFAW
, tRAS
):
35 self
.set_attributes(locals())
37 # SPD ----------------------------------------------------------------------------------------------
39 def _read_field(byte
, nbits
, shift
):
41 return (byte
& (mask
<< shift
)) >> shift
43 def _twos_complement(value
, nbits
):
44 if value
& (1 << (nbits
- 1)):
49 return (msb
<< 8) | lsb
55 def __init__(self
, spd_data
):
56 # Geometry ---------------------------------------------------------------------------------
62 }[_read_field(spd_data
[4], nbits
=3, shift
=4)]
69 }[_read_field(spd_data
[5], nbits
=3, shift
=3)]
75 }[_read_field(spd_data
[5], nbits
=3, shift
=0)]
77 self
.nbanks
= 2**bankbits
78 self
.nrows
= 2**rowbits
79 self
.ncols
= 2**colbits
81 # Timings ----------------------------------------------------------------------------------
82 self
.init_timebase(spd_data
)
84 # most signifficant (upper) / least signifficant (lower) nibble
86 return _read_field(byte
, nbits
=4, shift
=4)
89 return _read_field(byte
, nbits
=4, shift
=0)
92 tck_min
= self
.txx_ns(mtb
=b
[12], ftb
=b
[34])
93 taa_min
= self
.txx_ns(mtb
=b
[16], ftb
=b
[35])
94 twr_min
= self
.txx_ns(mtb
=b
[17])
95 trcd_min
= self
.txx_ns(mtb
=b
[18], ftb
=b
[36])
96 trrd_min
= self
.txx_ns(mtb
=b
[19])
97 trp_min
= self
.txx_ns(mtb
=b
[20], ftb
=b
[37])
98 tras_min
= self
.txx_ns(mtb
=_word(lsn(b
[21]), b
[22]))
99 trc_min
= self
.txx_ns(mtb
=_word(msn(b
[21]), b
[23]), ftb
=b
[38])
100 trfc_min
= self
.txx_ns(mtb
=_word(b
[25], b
[24]))
101 twtr_min
= self
.txx_ns(mtb
=b
[26])
102 trtp_min
= self
.txx_ns(mtb
=b
[27])
103 tfaw_min
= self
.txx_ns(mtb
=_word(lsn(b
[28]), b
[29]))
105 technology_timings
= _TechnologyTimings(
106 tREFI
= 64e6
/8192, # 64ms/8192ops
107 tWTR
= (4, twtr_min
), # min 4 cycles
108 tCCD
= (4, None), # min 4 cycles
109 tRRD
= (4, trrd_min
), # min 4 cycles
112 speedgrade_timings
= _SpeedgradeTimings(
116 tRFC
= (None, trfc_min
),
117 tFAW
= (None, tfaw_min
),
121 self
.speedgrade
= str(self
.speedgrade_freq(tck_min
))
122 self
.technology_timings
= technology_timings
123 self
.speedgrade_timings
= {
124 self
.speedgrade
: speedgrade_timings
,
125 "default": speedgrade_timings
,
128 def init_timebase(self
, data
):
129 # All the DDR3 timings are defined in the units of "timebase", which
130 # consists of medium timebase (nanosec) and fine timebase (picosec).
131 fine_timebase_dividend
= _read_field(data
[9], nbits
=4, shift
=4)
132 fine_timebase_divisor
= _read_field(data
[9], nbits
=4, shift
=0)
133 fine_timebase_ps
= fine_timebase_dividend
/ fine_timebase_divisor
134 self
.fine_timebase_ns
= fine_timebase_ps
* 1e-3
135 medium_timebase_dividend
= data
[10]
136 medium_timebase_divisor
= data
[11]
137 self
.medium_timebase_ns
= medium_timebase_dividend
/ medium_timebase_divisor
139 def txx_ns(self
, mtb
, ftb
=0):
140 """Get tXX in nanoseconds from medium and (optional) fine timebase."""
141 # decode FTB encoded in 8-bit two's complement
142 ftb
= _twos_complement(ftb
, 8)
143 return mtb
* self
.medium_timebase_ns
+ ftb
* self
.fine_timebase_ns
146 def speedgrade_freq(tck_ns
):
147 # Calculate rounded speedgrade frequency from tck_min
148 freq_mhz
= (1 / (tck_ns
* 1e-9)) / 1e6
149 freq_mhz
*= 2 # clock rate -> transfer rate (DDR)
150 speedgrades
= [800, 1066, 1333, 1600, 1866, 2133]
151 for f
in speedgrades
:
152 # Due to limited tck accuracy of 1ps, calculations may yield higher
153 # frequency than in reality (e.g. for DDR3-1866: tck=1.071 ns ->
154 # -> f=1867.4 MHz, while real is f=1866.6(6) MHz).
156 if abs(freq_mhz
- f
) < max_error
:
158 raise ValueError("Transfer rate = {:.2f} does not correspond to any DDR3 speedgrade"
161 def parse_spd_hexdump(filename
):
162 """Parse data dumped using the `spdread` command in LiteX BIOS
164 This will read files in format:
166 0x00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ................
167 0x00000010 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f ................
171 with
open(filename
) as f
:
173 if line
.startswith("0x"):
174 tokens
= line
.strip().split()
175 addr
= int(tokens
[0], 16)
176 assert addr
> last_addr
177 values
= [int(v
, 16) for v
in tokens
[1:17]]
182 # SDRAMModule --------------------------------------------------------------------------------------
185 """SDRAM module geometry and timings.
187 SDRAM controller has to ensure that all geometry and
188 timings parameters are fulfilled. Timings parameters
189 can be expressed in ns, in SDRAM clock cycles or both
190 and controller needs to use the greater value.
192 SDRAM modules with the same geometry exist can have
196 def __init__(self
, clk_freq
, rate
, speedgrade
=None, fine_refresh_mode
=None):
197 self
.clk_freq
= clk_freq
199 self
.speedgrade
= speedgrade
200 self
.geom_settings
= GeomSettings(
201 bankbits
= log2_int(self
.nbanks
),
202 rowbits
= log2_int(self
.nrows
),
203 colbits
= log2_int(self
.ncols
),
205 assert not (self
.memtype
!= "DDR4" and fine_refresh_mode
!= None)
206 assert fine_refresh_mode
in [None, "1x", "2x", "4x"]
207 if (fine_refresh_mode
is None) and (self
.memtype
== "DDR4"):
208 fine_refresh_mode
= "1x"
209 self
.timing_settings
= TimingSettings(
210 tRP
= self
.ns_to_cycles(self
.get("tRP")),
211 tRCD
= self
.ns_to_cycles(self
.get("tRCD")),
212 tWR
= self
.ns_to_cycles(self
.get("tWR")),
213 tREFI
= self
.ns_to_cycles(self
.get("tREFI", fine_refresh_mode
), False),
214 tRFC
= self
.ck_ns_to_cycles(*self
.get("tRFC", fine_refresh_mode
)),
215 tWTR
= self
.ck_ns_to_cycles(*self
.get("tWTR")),
216 tFAW
= None if self
.get("tFAW") is None else self
.ck_ns_to_cycles(*self
.get("tFAW")),
217 tCCD
= None if self
.get("tCCD") is None else self
.ck_ns_to_cycles(*self
.get("tCCD")),
218 tRRD
= None if self
.get("tRRD") is None else self
.ck_ns_to_cycles(*self
.get("tRRD")),
219 tRC
= None if self
.get("tRAS") is None else self
.ns_to_cycles(self
.get("tRP") + self
.get("tRAS")),
220 tRAS
= None if self
.get("tRAS") is None else self
.ns_to_cycles(self
.get("tRAS")),
221 tZQCS
= None if self
.get("tZQCS") is None else self
.ck_ns_to_cycles(*self
.get("tZQCS"))
223 self
.timing_settings
.fine_refresh_mode
= fine_refresh_mode
225 def get(self
, name
, key
=None):
227 if name
in _speedgrade_timings
:
228 if hasattr(self
, "speedgrade_timings"):
229 speedgrade
= "default" if self
.speedgrade
is None else self
.speedgrade
230 r
= getattr(self
.speedgrade_timings
[speedgrade
], name
)
232 name
= name
+ "_" + self
.speedgrade
if self
.speedgrade
is not None else name
234 r
= getattr(self
, name
)
238 if hasattr(self
, "technology_timings"):
239 r
= getattr(self
.technology_timings
, name
)
242 r
= getattr(self
, name
)
245 if (r
is not None) and (key
is not None):
249 def ns_to_cycles(self
, t
, margin
=True):
250 clk_period_ns
= 1e9
/self
.clk_freq
254 "1:2" : clk_period_ns
/2,
255 "1:4" : 3*clk_period_ns
/4
257 t
+= margins
[self
.rate
]
258 return ceil(t
/clk_period_ns
)
260 def ck_to_cycles(self
, c
):
266 return ceil(c
/d
[self
.rate
])
268 def ck_ns_to_cycles(self
, c
, t
):
269 c
= 0 if c
is None else c
270 t
= 0 if t
is None else t
271 return max(self
.ck_to_cycles(c
), self
.ns_to_cycles(t
))
274 def from_spd_data(cls
, spd_data
, clk_freq
, fine_refresh_mode
=None):
275 # set parameters from SPD data based on memory type
279 spd
= spd_cls(spd_data
)
281 # Create a deriving class to avoid modifying this one
282 class _SDRAMModule(cls
):
283 memtype
= spd
.memtype
287 technology_timings
= spd
.technology_timings
288 speedgrade_timings
= spd
.speedgrade_timings
298 rate
= "1:{}".format(nphases
)
300 return _SDRAMModule(clk_freq
,
302 speedgrade
= spd
.speedgrade
,
303 fine_refresh_mode
= fine_refresh_mode
)
305 class SDRAMRegisteredModule(SDRAMModule
): registered
= True
307 # SDR ----------------------------------------------------------------------------------------------
309 class SDRModule(SDRAMModule
): memtype
= "SDR"
310 class SDRRegisteredModule(SDRAMRegisteredModule
): memtype
= "SDR"
312 class IS42S16160(SDRModule
):
318 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=None)
319 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=20, tRCD
=20, tWR
=20, tRFC
=(None, 70), tFAW
=None, tRAS
=None)}
321 class IS42S16320(SDRModule
):
327 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=None)
328 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=20, tRCD
=20, tWR
=20, tRFC
=(None, 70), tFAW
=None, tRAS
=None)}
330 class MT48LC4M16(SDRModule
):
336 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=None)
337 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=14, tRFC
=(None, 66), tFAW
=None, tRAS
=None)}
339 class MT48LC16M16(SDRModule
):
345 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=(None, 15))
346 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=20, tRCD
=20, tWR
=15, tRFC
=(None, 66), tFAW
=None, tRAS
=44)}
348 class AS4C16M16(SDRModule
):
354 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=None)
355 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=18, tRCD
=18, tWR
=12, tRFC
=(None, 60), tFAW
=None, tRAS
=None)}
357 class AS4C32M16(SDRModule
):
363 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=None)
364 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=18, tRCD
=18, tWR
=12, tRFC
=(None, 60), tFAW
=None, tRAS
=None)}
366 class AS4C32M8(SDRModule
):
372 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=(None, 15))
373 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=20, tRCD
=20, tWR
=15, tRFC
=(None, 66), tFAW
=None, tRAS
=44)}
375 class M12L64322A(SDRModule
):
381 technology_timings
= _TechnologyTimings(tREFI
=64e6
/4096, tWTR
=(2, None), tCCD
=(1, None), tRRD
=(None, 10))
382 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 55), tFAW
=None, tRAS
=40)}
384 class M12L16161A(SDRModule
):
390 technology_timings
= _TechnologyTimings(tREFI
=64e6
/4096, tWTR
=(2, None), tCCD
=(1, None), tRRD
=(None, 10))
391 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 55), tFAW
=None, tRAS
=40)}
393 # DDR ----------------------------------------------------------------------------------------------
395 class DDRModule(SDRAMModule
): memtype
= "DDR"
396 class DDRRegisteredModule(SDRAMRegisteredModule
): memtype
= "DDR"
398 class MT46V32M16(SDRAMModule
):
405 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=None)
406 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 70), tFAW
=None, tRAS
=None)}
408 # LPDDR --------------------------------------------------------------------------------------------
410 class LPDDRModule(SDRAMModule
): memtype
= "LPDDR"
411 class LPDDRRegisteredModule(SDRAMRegisteredModule
): memtype
= "LPDDR"
413 class MT46H32M16(LPDDRModule
):
419 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=None)
420 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 72), tFAW
=None, tRAS
=None)}
422 class MT46H32M32(LPDDRModule
):
428 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(2, None), tCCD
=(1, None), tRRD
=None)
429 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 72), tFAW
=None, tRAS
=None)}
431 # DDR2 ---------------------------------------------------------------------------------------------
433 class DDR2Module(SDRAMModule
): memtype
= "DDR2"
434 class DDR2RegisteredModule(SDRAMRegisteredModule
): memtype
= "DDR2"
436 class MT47H128M8(DDR2Module
):
443 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(None, 7.5), tCCD
=(2, None), tRRD
=None)
444 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 127.5), tFAW
=None, tRAS
=None)}
446 class MT47H32M16(DDR2Module
):
453 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(None, 7.5), tCCD
=(2, None), tRRD
=None)
454 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 127.5), tFAW
=None, tRAS
=None)}
456 class MT47H64M16(DDR2Module
):
463 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(None, 7.5), tCCD
=(2, None), tRRD
=None)
464 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 127.5), tFAW
=None, tRAS
=None)}
466 class P3R1GE4JGF(DDR2Module
):
473 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(None, 7.5), tCCD
=(2, None), tRRD
=None)
474 speedgrade_timings
= {"default": _SpeedgradeTimings(tRP
=12.5, tRCD
=12.5, tWR
=15, tRFC
=(None, 127.5), tFAW
=None, tRAS
=None)}
476 # DDR3 (Chips) -------------------------------------------------------------------------------------
478 class DDR3Module(SDRAMModule
): memtype
= "DDR3"
479 class DDR3RegisteredModule(SDRAMRegisteredModule
): memtype
= "DDR3"
481 class MT41K64M16(DDR3Module
):
488 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 10), tZQCS
=(64, 80))
489 speedgrade_timings
= {
490 "800": _SpeedgradeTimings(tRP
=13.1, tRCD
=13.1, tWR
=13.1, tRFC
=(64, None), tFAW
=(None, 50), tRAS
=37.5),
491 "1066": _SpeedgradeTimings(tRP
=13.1, tRCD
=13.1, tWR
=13.1, tRFC
=(86, None), tFAW
=(None, 50), tRAS
=37.5),
492 "1333": _SpeedgradeTimings(tRP
=13.5, tRCD
=13.5, tWR
=13.5, tRFC
=(107, None), tFAW
=(None, 45), tRAS
=36),
493 "1600": _SpeedgradeTimings(tRP
=13.75, tRCD
=13.75, tWR
=13.75, tRFC
=(128, None), tFAW
=(None, 40), tRAS
=35),
495 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
497 class MT41J128M16(DDR3Module
):
504 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 10), tZQCS
=(64, 80))
505 speedgrade_timings
= {
506 "800": _SpeedgradeTimings(tRP
=13.1, tRCD
=13.1, tWR
=13.1, tRFC
=(64, None), tFAW
=(None, 50), tRAS
=37.5),
507 "1066": _SpeedgradeTimings(tRP
=13.1, tRCD
=13.1, tWR
=13.1, tRFC
=(86, None), tFAW
=(None, 50), tRAS
=37.5),
508 "1333": _SpeedgradeTimings(tRP
=13.5, tRCD
=13.5, tWR
=13.5, tRFC
=(107, None), tFAW
=(None, 45), tRAS
=36),
509 "1600": _SpeedgradeTimings(tRP
=13.75, tRCD
=13.75, tWR
=13.75, tRFC
=(128, None), tFAW
=(None, 40), tRAS
=35),
511 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
513 class MT41K128M16(MT41J128M16
): pass
515 class MT41J256M16(DDR3Module
):
521 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 10), tZQCS
=(64, 80))
522 speedgrade_timings
= {
523 "800": _SpeedgradeTimings(tRP
=13.1, tRCD
=13.1, tWR
=13.1, tRFC
=(139, None), tFAW
=(None, 50), tRAS
=37.5),
524 "1066": _SpeedgradeTimings(tRP
=13.1, tRCD
=13.1, tWR
=13.1, tRFC
=(138, None), tFAW
=(None, 50), tRAS
=37.5),
525 "1333": _SpeedgradeTimings(tRP
=13.5, tRCD
=13.5, tWR
=13.5, tRFC
=(174, None), tFAW
=(None, 45), tRAS
=36),
526 "1600": _SpeedgradeTimings(tRP
=13.75, tRCD
=13.75, tWR
=13.75, tRFC
=(208, None), tFAW
=(None, 40), tRAS
=35),
528 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
530 class MT41K256M16(MT41J256M16
): pass
532 class MT41J512M16(DDR3Module
):
538 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 10), tZQCS
=(64, 80))
539 speedgrade_timings
= {
540 "1600": _SpeedgradeTimings(tRP
=13.75, tRCD
=13.75, tWR
=13.75, tRFC
=(280, None), tFAW
=(None, 40), tRAS
=39),
542 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
544 class MT41K512M16(MT41J512M16
): pass
546 class K4B1G0446F(DDR3Module
):
552 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 10), tZQCS
=(64, 80))
553 speedgrade_timings
= {
554 "800": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(120, None), tFAW
=(None, 50), tRAS
=37.5),
555 "1066": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(160, None), tFAW
=(None, 50), tRAS
=37.5),
556 "1333": _SpeedgradeTimings(tRP
=13.5, tRCD
=13.5, tWR
=15, tRFC
=(200, None), tFAW
=(None, 45), tRAS
=36),
557 "1600": _SpeedgradeTimings(tRP
=13.75, tRCD
=13.75, tWR
=15, tRFC
=(240, None), tFAW
=(None, 40), tRAS
=35),
559 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
561 class K4B2G1646F(DDR3Module
):
567 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 10), tZQCS
=(64, 80))
568 speedgrade_timings
= {
569 "800": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(104, None), tFAW
=(None, 50), tRAS
=37.5),
570 "1066": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(139, None), tFAW
=(None, 50), tRAS
=37.5),
571 "1333": _SpeedgradeTimings(tRP
=13.5, tRCD
=13.5, tWR
=15, tRFC
=(174, None), tFAW
=(None, 45), tRAS
=36),
572 "1600": _SpeedgradeTimings(tRP
=13.75, tRCD
=13.75, tWR
=15, tRFC
=(208, None), tFAW
=(None, 40), tRAS
=35),
574 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
576 class H5TC4G63CFR(DDR3Module
):
582 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 7.5), tZQCS
=(64, 80))
583 speedgrade_timings
= {
584 "800": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(260, None), tFAW
=(None, 40), tRAS
=37.5),
586 speedgrade_timings
["default"] = speedgrade_timings
["800"]
588 class IS43TR16128B(DDR3Module
):
594 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 6), tZQCS
=(64, 80))
595 speedgrade_timings
= {
596 "1600": _SpeedgradeTimings(tRP
=13.75, tRCD
=13.75, tWR
=15, tRFC
=(None, 160), tFAW
=(None, 40), tRAS
=35),
598 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
601 # DDR3 (SO-DIMM) -----------------------------------------------------------------------------------
603 class MT8JTF12864(DDR3Module
):
604 # base chip: MT41J128M8
610 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 6), tZQCS
=(64, 80))
611 speedgrade_timings
= {
612 "1066": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 110), tFAW
=(None, 37.5), tRAS
=37.5),
613 "1333": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(None, 110), tFAW
=(None, 30), tRAS
=36),
615 speedgrade_timings
["default"] = speedgrade_timings
["1333"]
617 class MT8KTF51264(DDR3Module
):
618 # base chip: MT41K512M8
624 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 6), tZQCS
=(64, 80))
625 speedgrade_timings
= {
626 "800" : _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 40), tRAS
=37.5),
627 "1066": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 40), tRAS
=37.5),
628 "1333": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 30), tRAS
=36),
629 "1600": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 30), tRAS
=35),
630 "1866": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 27), tRAS
=34),
632 speedgrade_timings
["default"] = speedgrade_timings
["1866"]
634 class MT18KSF1G72HZ(DDR3Module
):
635 # base chip: MT41K512M8
641 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 6), tZQCS
=(64, 80))
642 speedgrade_timings
= {
643 "1066": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 40), tRAS
=37.5),
644 "1333": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 30), tRAS
=36),
645 "1600": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 30), tRAS
=35),
647 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
649 class AS4C256M16D3A(DDR3Module
):
655 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 7.5), tZQCS
=(64, 80))
656 speedgrade_timings
= {
657 "1600": _SpeedgradeTimings(tRP
=13.75, tRCD
=13.75, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 40), tRAS
=35),
659 speedgrade_timings
["default"] = speedgrade_timings
["1600"]
661 class MT16KTF1G64HZ(DDR3Module
):
662 # base chip: MT41K512M8
668 technology_timings
= _TechnologyTimings(tREFI
=64e6
/8192, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 6), tZQCS
=(64, 80))
669 speedgrade_timings
= {
670 "800" : _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 40), tRAS
=37.5),
671 "1066": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 40), tRAS
=37.5),
672 "1333": _SpeedgradeTimings(tRP
=15, tRCD
=15, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 30), tRAS
=36),
673 "1600": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 30), tRAS
=35),
674 "1866": _SpeedgradeTimings(tRP
=13.125, tRCD
=13.125, tWR
=15, tRFC
=(None, 260), tFAW
=(None, 27), tRAS
=34),
676 speedgrade_timings
["default"] = speedgrade_timings
["1866"]
679 # DDR4 (Chips) -------------------------------------------------------------------------------------
681 class DDR4Module(SDRAMModule
): memtype
= "DDR4"
682 class DDR4RegisteredModule(SDRAMRegisteredModule
): memtype
= "DDR4"
684 class EDY4016A(DDR4Module
):
688 nbanks
= ngroups
* ngroupbanks
692 trefi
= {"1x": 64e6
/8192, "2x": (64e6
/8192)/2, "4x": (64e6
/8192)/4}
693 trfc
= {"1x": (None, 260), "2x": (None, 160), "4x": (None, 110)}
694 technology_timings
= _TechnologyTimings(tREFI
=trefi
, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 4.9), tZQCS
=(128, 80))
695 speedgrade_timings
= {
696 "2400": _SpeedgradeTimings(tRP
=13.32, tRCD
=13.32, tWR
=15, tRFC
=trfc
, tFAW
=(28, 30), tRAS
=32),
698 speedgrade_timings
["default"] = speedgrade_timings
["2400"]
700 class MT40A1G8(DDR4Module
):
704 nbanks
= ngroups
* ngroupbanks
708 trefi
= {"1x": 64e6
/8192, "2x": (64e6
/8192)/2, "4x": (64e6
/8192)/4}
709 trfc
= {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
710 technology_timings
= _TechnologyTimings(tREFI
=trefi
, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 6.4), tZQCS
=(128, 80))
711 speedgrade_timings
= {
712 "2400": _SpeedgradeTimings(tRP
=13.32, tRCD
=13.32, tWR
=15, tRFC
=trfc
, tFAW
=(20, 25), tRAS
=32),
713 "2666": _SpeedgradeTimings(tRP
=13.50, tRCD
=13.50, tWR
=15, tRFC
=trfc
, tFAW
=(20, 21), tRAS
=32),
715 speedgrade_timings
["default"] = speedgrade_timings
["2400"]
717 class MT40A256M16(DDR4Module
):
721 nbanks
= ngroups
* ngroupbanks
725 trefi
= {"1x": 64e6
/8192, "2x": (64e6
/8192)/2, "4x": (64e6
/8192)/4}
726 trfc
= {"1x": (None, 260), "2x": (None, 160), "4x": (None, 110)}
727 technology_timings
= _TechnologyTimings(tREFI
=trefi
, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 4.9), tZQCS
=(128, 80))
728 speedgrade_timings
= {
729 "2400": _SpeedgradeTimings(tRP
=13.32, tRCD
=13.32, tWR
=15, tRFC
=trfc
, tFAW
=(28, 35), tRAS
=32),
731 speedgrade_timings
["default"] = speedgrade_timings
["2400"]
733 class MT40A512M8(DDR4Module
):
737 nbanks
= ngroups
* ngroupbanks
741 trefi
= {"1x": 64e6
/8192, "2x": (64e6
/8192)/2, "4x": (64e6
/8192)/4}
742 trfc
= {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
743 technology_timings
= _TechnologyTimings(tREFI
=trefi
, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 4.9), tZQCS
=(128, 80))
744 speedgrade_timings
= {
745 "2400": _SpeedgradeTimings(tRP
=13.32, tRCD
=13.32, tWR
=15, tRFC
=trfc
, tFAW
=(20, 25), tRAS
=32),
746 "2666": _SpeedgradeTimings(tRP
=13.50, tRCD
=13.50, tWR
=15, tRFC
=trfc
, tFAW
=(20, 21), tRAS
=32),
748 speedgrade_timings
["default"] = speedgrade_timings
["2400"]
750 class MT40A512M16(DDR4Module
):
754 nbanks
= ngroups
* ngroupbanks
758 trefi
= {"1x": 64e6
/8192, "2x": (64e6
/8192)/2, "4x": (64e6
/8192)/4}
759 trfc
= {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
760 technology_timings
= _TechnologyTimings(tREFI
=trefi
, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 4.9), tZQCS
=(128, 80))
761 speedgrade_timings
= {
762 "2400": _SpeedgradeTimings(tRP
=13.32, tRCD
=13.32, tWR
=15, tRFC
=trfc
, tFAW
=(20, 25), tRAS
=32),
764 speedgrade_timings
["default"] = speedgrade_timings
["2400"]
766 # DDR4 (SO-DIMM) -----------------------------------------------------------------------------------
768 class KVR21SE15S84(DDR4Module
):
772 nbanks
= ngroups
* ngroupbanks
776 trefi
= {"1x": 64e6
/8192, "2x": (64e6
/8192)/2, "4x": (64e6
/8192)/4}
777 trfc
= {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
778 technology_timings
= _TechnologyTimings(tREFI
=trefi
, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 4.9), tZQCS
=(128, 80))
779 speedgrade_timings
= {
780 "2133": _SpeedgradeTimings(tRP
=13.5, tRCD
=13.5, tWR
=15, tRFC
=trfc
, tFAW
=(20, 25), tRAS
=33),
782 speedgrade_timings
["default"] = speedgrade_timings
["2133"]
784 class MTA4ATF51264HZ(DDR4Module
):
788 nbanks
= ngroups
* ngroupbanks
792 trefi
= {"1x": 64e6
/8192, "2x": (64e6
/8192)/2, "4x": (64e6
/8192)/4}
793 trfc
= {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
794 technology_timings
= _TechnologyTimings(tREFI
=trefi
, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 4.9), tZQCS
=(128, 80))
795 speedgrade_timings
= {
796 "2133": _SpeedgradeTimings(tRP
=13.5, tRCD
=13.5, tWR
=15, tRFC
=trfc
, tFAW
=(20, 25), tRAS
=33),
798 speedgrade_timings
["default"] = speedgrade_timings
["2133"]
800 # DDR4 (RDIMM) -------------------------------------------------------------------------------------
802 class MTA18ASF2G72PZ(DDR4RegisteredModule
):
806 nbanks
= ngroups
* ngroupbanks
810 trefi
= {"1x": 64e6
/8192, "2x": (64e6
/8192)/2, "4x": (64e6
/8192)/4}
811 trfc
= {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
812 technology_timings
= _TechnologyTimings(tREFI
=trefi
, tWTR
=(4, 7.5), tCCD
=(4, None), tRRD
=(4, 4.9), tZQCS
=(128, 80))
813 speedgrade_timings
= {
814 "2400": _SpeedgradeTimings(tRP
=13.32, tRCD
=13.32, tWR
=15, tRFC
=trfc
, tFAW
=(20, 25), tRAS
=32),
816 speedgrade_timings
["default"] = speedgrade_timings
["2400"]