gram/phy/ecp5ddrphy.py

   1 # This file is Copyright (c) 2019 David Shah <dave@ds0.me>
   2 # This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   4 # License: BSD
   5
   6 # 1:2 frequency-ratio DDR3 PHY for Lattice's ECP5
   7 # DDR3: 800 MT/s
   8
   9 import math
  10
  11 from nmigen import *
  12 from nmigen.lib.cdc import FFSynchronizer
  13 from nmigen.utils import log2_int
  14
  15 from lambdasoc.periph import Peripheral
  16
  17 import gram.stream as stream
  18 from gram.common import *
  19 from gram.phy.dfi import Interface
  20 from gram.compat import Timeline
  21
  22 # Lattice ECP5 DDR PHY Initialization --------------------------------------------------------------
  23
  24
  25 class ECP5DDRPHYInit(Elaboratable):
  26     def __init__(self):
  27         self.pause = Signal()
  28         self.stop = Signal()
  29         self.delay = Signal()
  30         self.reset = Signal()
  31
  32     def elaborate(self, platform):
  33         m = Module()
  34
  35         new_lock = Signal()
  36         update = Signal()
  37         freeze = Signal()
  38
  39         # DDRDLLA instance -------------------------------------------------------------------------
  40         _lock = Signal()
  41         delay = Signal()
  42         m.submodules += Instance("DDRDLLA",
  43                                  i_CLK=ClockSignal("sync2x"),
  44                                  i_RST=ResetSignal("init"),
  45                                  i_UDDCNTLN=~update,
  46                                  i_FREEZE=freeze,
  47                                  o_DDRDEL=delay,
  48                                  o_LOCK=_lock
  49                                  )
  50         lock = Signal()
  51         lock_d = Signal()
  52         m.submodules += FFSynchronizer(_lock, lock, o_domain="init")
  53         m.d.init += lock_d.eq(lock)
  54         m.d.sync += new_lock.eq(lock & ~lock_d)
  55
  56         # DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
  57         t = 8  # in cycles
  58         tl = Timeline([
  59             (1*t,  [freeze.eq(1)]),  # Freeze DDRDLLA
  60             (2*t,  [self.stop.eq(1)]),   # Stop ECLK domain
  61             (3*t,  [self.reset.eq(1)]),  # Reset ECLK domain
  62             (4*t,  [self.reset.eq(0)]),  # Release ECLK domain reset
  63             (5*t,  [self.stop.eq(0)]),   # Release ECLK domain stop
  64             (6*t,  [freeze.eq(0)]),  # Release DDRDLLA freeze
  65             (7*t,  [self.pause.eq(1)]),  # Pause DQSBUFM
  66             (8*t,  [update.eq(1)]),  # Update DDRDLLA
  67             (9*t,  [update.eq(0)]),  # Release DDRDMMA update
  68             (10*t, [self.pause.eq(0)]),  # Release DQSBUFM pause
  69         ])
  70         m.submodules += tl
  71         # Wait DDRDLLA Lock
  72         m.d.comb += tl.trigger.eq(new_lock)
  73
  74         m.d.comb += self.delay.eq(delay)
  75
  76         return m
  77
  78 # Lattice ECP5 DDR PHY -----------------------------------------------------------------------------
  79
  80
  81 class ECP5DDRPHY(Peripheral, Elaboratable):
  82     def __init__(self, pads, sys_clk_freq=100e6):
  83         super().__init__(name="phy")
  84
  85         self.pads = pads
  86         self._sys_clk_freq = sys_clk_freq
  87
  88         databits = len(self.pads.dq.io)
  89         assert databits % 8 == 0
  90
  91         # CSR
  92         bank = self.csr_bank()
  93
  94         self._dly_sel = bank.csr(databits//8, "rw")
  95
  96         self._rdly_dq_rst = bank.csr(1, "rw")
  97         self._rdly_dq_inc = bank.csr(1, "rw")
  98         self._rdly_dq_bitslip_rst = bank.csr(1, "rw")
  99         self._rdly_dq_bitslip = bank.csr(1, "rw")
 100
 101         self._burstdet_clr = bank.csr(1, "rw")
 102         self._burstdet_seen = bank.csr(databits//8, "r")
 103
 104         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
 105         self.bus = self._bridge.bus
 106
 107         addressbits = len(self.pads.a.o0)
 108         bankbits = len(self.pads.ba.o0)
 109         nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0)
 110         databits = len(self.pads.dq.io)
 111         self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
 112
 113         # PHY settings -----------------------------------------------------------------------------
 114         tck = 2/(2*2*self._sys_clk_freq)
 115         nphases = 2
 116         databits = len(self.pads.dq.io)
 117         nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0)
 118         cl, cwl = get_cl_cw("DDR3", tck)
 119         cl_sys_latency = get_sys_latency(nphases, cl)
 120         cwl_sys_latency = get_sys_latency(nphases, cwl)
 121         rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
 122         wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
 123         self.settings = PhySettings(
 124             phytype="ECP5DDRPHY",
 125             memtype="DDR3",
 126             databits=databits,
 127             dfi_databits=4*databits,
 128             nranks=nranks,
 129             nphases=nphases,
 130             rdphase=rdphase,
 131             wrphase=wrphase,
 132             rdcmdphase=rdcmdphase,
 133             wrcmdphase=wrcmdphase,
 134             cl=cl,
 135             cwl=cwl,
 136             read_latency=2 + cl_sys_latency + 2 + log2_int(4//nphases) + 4,
 137             write_latency=cwl_sys_latency
 138         )
 139
 140     def elaborate(self, platform):
 141         m = Module()
 142
 143         m.submodules.bridge = self._bridge
 144
 145         tck = 2/(2*2*self._sys_clk_freq)
 146         nphases = 2
 147         databits = len(self.pads.dq.io)
 148
 149         # Init -------------------------------------------------------------------------------------
 150         m.submodules.init = init = ECP5DDRPHYInit()
 151
 152         # Parameters -------------------------------------------------------------------------------
 153         cl, cwl = get_cl_cw("DDR3", tck)
 154         cl_sys_latency = get_sys_latency(nphases, cl)
 155         cwl_sys_latency = get_sys_latency(nphases, cwl)
 156
 157         # Observation
 158         self.datavalid = Signal(databits//8)
 159
 160         # DFI Interface ----------------------------------------------------------------------------
 161         dfi = self.dfi
 162
 163         bl8_chunk = Signal()
 164
 165         # Clock --------------------------------------------------------------------------------
 166         m.d.comb += [
 167             self.pads.clk.o_clk.eq(ClockSignal("dramsync")),
 168             self.pads.clk.o_fclk.eq(ClockSignal("sync2x")),
 169         ]
 170         for i in range(len(self.pads.clk.o0)):
 171             m.d.comb += [
 172                 self.pads.clk.o0[i].eq(0),
 173                 self.pads.clk.o1[i].eq(1),
 174                 self.pads.clk.o2[i].eq(0),
 175                 self.pads.clk.o3[i].eq(1),
 176             ]
 177
 178         # Addresses and Commands ---------------------------------------------------------------
 179         m.d.comb += [
 180             self.pads.a.o_clk.eq(ClockSignal("dramsync")),
 181             self.pads.a.o_fclk.eq(ClockSignal("sync2x")),
 182             self.pads.ba.o_clk.eq(ClockSignal("dramsync")),
 183             self.pads.ba.o_fclk.eq(ClockSignal("sync2x")),
 184         ]
 185         for i in range(len(self.pads.a.o0)):
 186             m.d.comb += [
 187                 self.pads.a.o0[i].eq(dfi.phases[0].address[i]),
 188                 self.pads.a.o1[i].eq(dfi.phases[0].address[i]),
 189                 self.pads.a.o2[i].eq(dfi.phases[1].address[i]),
 190                 self.pads.a.o3[i].eq(dfi.phases[1].address[i]),
 191             ]
 192         for i in range(len(self.pads.ba.o0)):
 193             m.d.comb += [
 194                 self.pads.ba.o0[i].eq(dfi.phases[0].bank[i]),
 195                 self.pads.ba.o1[i].eq(dfi.phases[0].bank[i]),
 196                 self.pads.ba.o2[i].eq(dfi.phases[1].bank[i]),
 197                 self.pads.ba.o3[i].eq(dfi.phases[1].bank[i]),
 198             ]
 199
 200         controls = ["ras", "cas", "we", "clk_en", "odt"]
 201         if hasattr(self.pads, "reset"):
 202             controls.append("reset")
 203         if hasattr(self.pads, "cs"):
 204             controls.append("cs")
 205         for name in controls:
 206             m.d.comb += [
 207                 getattr(self.pads, name).o_clk.eq(ClockSignal("dramsync")),
 208                 getattr(self.pads, name).o_fclk.eq(ClockSignal("sync2x")),
 209             ]
 210             for i in range(len(getattr(self.pads, name).o0)):
 211                 m.d.comb += [
 212                     getattr(self.pads, name).o0[i].eq(getattr(dfi.phases[0], name)[i]),
 213                     getattr(self.pads, name).o1[i].eq(getattr(dfi.phases[0], name)[i]),
 214                     getattr(self.pads, name).o2[i].eq(getattr(dfi.phases[1], name)[i]),
 215                     getattr(self.pads, name).o3[i].eq(getattr(dfi.phases[1], name)[i]),
 216                 ]
 217
 218         # DQ ---------------------------------------------------------------------------------------
 219         dq_oe = Signal()
 220         dqs_oe = Signal()
 221         dqs_postamble = Signal()
 222         dqs_preamble = Signal()
 223         for i in range(databits//8):
 224             # DQSBUFM
 225             dqs_i = Signal()
 226             dqsr90 = Signal()
 227             dqsw270 = Signal()
 228             dqsw = Signal()
 229             rdpntr = Signal(3)
 230             wrpntr = Signal(3)
 231             rdly = Signal(7)
 232             burstdet = Signal()
 233
 234             m.submodules += Instance("DQSBUFM",
 235                                      p_DQS_LI_DEL_ADJ="MINUS",
 236                                      p_DQS_LI_DEL_VAL=1,
 237                                      p_DQS_LO_DEL_ADJ="MINUS",
 238                                      p_DQS_LO_DEL_VAL=4,
 239
 240                                      # Delay
 241                                      i_DYNDELAY0=0,
 242                                      i_DYNDELAY1=0,
 243                                      i_DYNDELAY2=0,
 244                                      i_DYNDELAY3=0,
 245                                      i_DYNDELAY4=0,
 246                                      i_DYNDELAY5=0,
 247                                      i_DYNDELAY6=0,
 248                                      i_DYNDELAY7=0,
 249
 250                                      # Clocks / Reset
 251                                      i_SCLK=ClockSignal("sync"),
 252                                      i_ECLK=ClockSignal("sync2x"),
 253                                      i_RST=ResetSignal("dramsync"),
 254                                      i_DDRDEL=init.delay,
 255                                      i_PAUSE=init.pause | self._dly_sel.w_data[i],
 256
 257                                      # Control
 258                                      # Assert LOADNs to use DDRDEL control
 259                                      i_RDLOADN=0,
 260                                      i_RDMOVE=0,
 261                                      i_RDDIRECTION=1,
 262                                      i_WRLOADN=0,
 263                                      i_WRMOVE=0,
 264                                      i_WRDIRECTION=1,
 265
 266                                      # Reads (generate shifted DQS clock for reads)
 267                                      i_READ0=1,
 268                                      i_READ1=1,
 269                                      i_READCLKSEL0=rdly[0],
 270                                      i_READCLKSEL1=rdly[1],
 271                                      i_READCLKSEL2=rdly[2],
 272                                      i_DQSI=dqs_i,
 273                                      o_DQSR90=dqsr90,
 274                                      o_RDPNTR0=rdpntr[0],
 275                                      o_RDPNTR1=rdpntr[1],
 276                                      o_RDPNTR2=rdpntr[2],
 277                                      o_WRPNTR0=wrpntr[0],
 278                                      o_WRPNTR1=wrpntr[1],
 279                                      o_WRPNTR2=wrpntr[2],
 280                                      o_DATAVALID=self.datavalid[i],
 281                                      o_BURSTDET=burstdet,
 282
 283                                      # Writes (generate shifted ECLK clock for writes)
 284                                      o_DQSW270=dqsw270,
 285                                      o_DQSW=dqsw)
 286             burstdet_d = Signal()
 287             m.d.sync += burstdet_d.eq(burstdet)
 288             with m.If(self._burstdet_clr.w_stb):
 289                 m.d.sync += self._burstdet_seen.r_data[i].eq(0)
 290             with m.If(burstdet & ~burstdet_d):
 291                 m.d.sync += self._burstdet_seen.r_data[i].eq(1)
 292
 293             # DQS and DM ---------------------------------------------------------------------------
 294             dm_o_data = Signal(8)
 295             dm_o_data_d = Signal(8)
 296             dm_o_data_muxed = Signal(4)
 297             m.d.comb += dm_o_data.eq(Cat(
 298                 dfi.phases[0].wrdata_mask[0*databits//8+i],
 299                 dfi.phases[0].wrdata_mask[1*databits//8+i],
 300                 dfi.phases[0].wrdata_mask[2*databits//8+i],
 301                 dfi.phases[0].wrdata_mask[3*databits//8+i],
 302
 303                 dfi.phases[1].wrdata_mask[0*databits//8+i],
 304                 dfi.phases[1].wrdata_mask[1*databits//8+i],
 305                 dfi.phases[1].wrdata_mask[2*databits//8+i],
 306                 dfi.phases[1].wrdata_mask[3*databits//8+i]),
 307             )
 308             m.d.sync += dm_o_data_d.eq(dm_o_data)
 309
 310             with m.If(bl8_chunk):
 311                 m.d.sync += dm_o_data_muxed.eq(dm_o_data_d[4:])
 312             with m.Else():
 313                 m.d.sync += dm_o_data_muxed.eq(dm_o_data[:4])
 314
 315             dm_o_data_muxed_d = Signal(4)
 316             m.d.sync += dm_o_data_muxed_d.eq(dm_o_data_muxed)
 317
 318             m.submodules += Instance("ODDRX2DQA",
 319                 i_RST=ResetSignal("dramsync"),
 320                 i_ECLK=ClockSignal("sync2x"),
 321                 i_SCLK=ClockSignal("dramsync"),
 322                 i_DQSW270=dqsw270,
 323                 i_D2=dm_o_data_muxed[0],
 324                 i_D3=dm_o_data_muxed[1],
 325                 i_D0=dm_o_data_muxed_d[2],
 326                 i_D1=dm_o_data_muxed_d[3],
 327                 o_Q=self.pads.dm.o[i])
 328
 329             dqs = Signal()
 330             dqs_oe_n = Signal()
 331             m.submodules += [
 332                 Instance("ODDRX2DQSB",
 333                          i_RST=ResetSignal("dramsync"),
 334                          i_ECLK=ClockSignal("sync2x"),
 335                          i_SCLK=ClockSignal(),
 336                          i_DQSW=dqsw,
 337                          i_D0=0,
 338                          i_D1=1,
 339                          i_D2=0,
 340                          i_D3=1,
 341                          o_Q=dqs
 342                          ),
 343                 Instance("TSHX2DQSA",
 344                          i_RST=ResetSignal("dramsync"),
 345                          i_ECLK=ClockSignal("sync2x"),
 346                          i_SCLK=ClockSignal(),
 347                          i_DQSW=dqsw,
 348                          i_T0=~(dqs_oe | dqs_postamble),
 349                          i_T1=~(dqs_oe | dqs_postamble),
 350                          o_Q=dqs_oe_n
 351                          ),
 352                 Instance("BB",
 353                     i_I=dqs,
 354                     i_T=dqs_oe_n,
 355                     o_O=dqs_i,
 356                     io_B=self.pads.dqs.io[i]
 357                     )
 358             ]
 359
 360             for j in range(8*i, 8*(i+1)):
 361                 dq_o = Signal()
 362                 dq_i = Signal()
 363                 dq_oe_n = Signal()
 364                 dq_i_delayed = Signal()
 365                 dq_i_data = Signal(4)
 366                 dq_o_data = Signal(8)
 367                 dq_o_data_d = Signal(8)
 368                 dq_o_data_muxed = Signal(4)
 369                 m.d.comb += dq_o_data.eq(Cat(
 370                     dfi.phases[0].wrdata[0*databits+j],
 371                     dfi.phases[0].wrdata[1*databits+j],
 372                     dfi.phases[0].wrdata[2*databits+j],
 373                     dfi.phases[0].wrdata[3*databits+j],
 374                     dfi.phases[1].wrdata[0*databits+j],
 375                     dfi.phases[1].wrdata[1*databits+j],
 376                     dfi.phases[1].wrdata[2*databits+j],
 377                     dfi.phases[1].wrdata[3*databits+j])
 378                 )
 379
 380                 m.d.sync += dq_o_data_d.eq(dq_o_data)
 381                 with m.Switch(bl8_chunk):
 382                     with m.Case(0):
 383                         m.d.sync += dq_o_data_muxed.eq(dq_o_data[:4])
 384                     with m.Case(1):
 385                         m.d.sync += dq_o_data_muxed.eq(dq_o_data_d[4:])
 386
 387                 dq_o_data_muxed_d = Signal.like(dq_o_data_muxed)
 388                 m.d.sync += dq_o_data_muxed_d.eq(dq_o_data_muxed)
 389
 390                 m.submodules += [
 391                     Instance("ODDRX2DQA",
 392                              i_RST=ResetSignal("dramsync"),
 393                              i_ECLK=ClockSignal("sync2x"),
 394                              i_SCLK=ClockSignal(),
 395                              i_DQSW270=dqsw270,
 396                              i_D0=dq_o_data_muxed_d[2],
 397                              i_D1=dq_o_data_muxed_d[3],
 398                              i_D2=dq_o_data_muxed[0],
 399                              i_D3=dq_o_data_muxed[1],
 400                              o_Q=dq_o
 401                              ),
 402                     Instance("DELAYF",
 403                              p_DEL_MODE="DQS_ALIGNED_X2",
 404                              i_LOADN=1,
 405                              i_MOVE=0,
 406                              i_DIRECTION=0,
 407                              i_A=dq_i,
 408                              o_Z=dq_i_delayed
 409                              ),
 410                     Instance("IDDRX2DQA",
 411                              i_RST=ResetSignal("dramsync"),
 412                              i_ECLK=ClockSignal("sync2x"),
 413                              i_SCLK=ClockSignal(),
 414                              i_DQSR90=dqsr90,
 415                              i_RDPNTR0=rdpntr[0],
 416                              i_RDPNTR1=rdpntr[1],
 417                              i_RDPNTR2=rdpntr[2],
 418                              i_WRPNTR0=wrpntr[0],
 419                              i_WRPNTR1=wrpntr[1],
 420                              i_WRPNTR2=wrpntr[2],
 421                              i_D=dq_i_delayed,
 422                              o_Q0=dq_i_data[0],
 423                              o_Q1=dq_i_data[1],
 424                              o_Q2=dq_i_data[2],
 425                              o_Q3=dq_i_data[3],
 426                              ),
 427                 ]
 428                 m.submodules += [
 429                     Instance("TSHX2DQA",
 430                              i_RST=ResetSignal("dramsync"),
 431                              i_ECLK=ClockSignal("sync2x"),
 432                              i_SCLK=ClockSignal(),
 433                              i_DQSW270=dqsw270,
 434                              i_T0=~dq_oe,
 435                              i_T1=~dq_oe,
 436                              o_Q=dq_oe_n,
 437                              ),
 438                     Instance("BB",
 439                         i_I=dq_o,
 440                         i_T=dq_oe_n,
 441                         o_O=dq_i,
 442                         io_B=self.pads.dq.io[j]
 443                         )
 444                 ]
 445                 m.d.sync += [
 446                     dfi.phases[1].rddata[j].eq(dq_i_data[0]),
 447                     dfi.phases[1].rddata[1*databits+j].eq(dq_i_data[1]),
 448                     dfi.phases[1].rddata[2*databits+j].eq(dq_i_data[2]),
 449                     dfi.phases[1].rddata[3*databits+j].eq(dq_i_data[3]),
 450                 ]
 451         m.d.sync += [
 452             dfi.phases[0].rddata.eq(dfi.phases[1].rddata),
 453         ]
 454
 455         # Read Control Path ------------------------------------------------------------------------
 456         # Creates a shift register of read commands coming from the DFI interface. This shift register
 457         # is used to control DQS read (internal read pulse of the DQSBUF) and to indicate to the
 458         # DFI interface that the read data is valid.
 459         #
 460         # The DQS read must be asserted for 2 sys_clk cycles before the read data is coming back from
 461         # the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2)
 462         #
 463         # The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI
 464         # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies.
 465         rddata_en = Signal(self.settings.read_latency)
 466         rddata_en_last = Signal.like(rddata_en)
 467         m.d.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last))
 468         m.d.sync += rddata_en_last.eq(rddata_en)
 469         m.d.sync += [phase.rddata_valid.eq(rddata_en[-1]) for phase in dfi.phases]
 470
 471         # Write Control Path -----------------------------------------------------------------------
 472         # Creates a shift register of write commands coming from the DFI interface. This shift register
 473         # is used to control DQ/DQS tristates and to select write data of the DRAM burst from the DFI
 474         # interface: The PHY is operating in halfrate mode (so provide 4 datas every sys_clk cycles:
 475         # 2x for DDR, 2x for halfrate) but DDR3 requires a burst of 8 datas (BL8) for best efficiency.
 476         # Writes are then performed in 2 sys_clk cycles and data needs to be selected for each cycle.
 477         # FIXME: understand +2
 478         wrdata_en = Signal(cwl_sys_latency + 5)
 479         wrdata_en_last = Signal.like(wrdata_en)
 480         m.d.comb += wrdata_en.eq(Cat(dfi.phases[self.settings.wrphase].wrdata_en, wrdata_en_last))
 481         m.d.sync += wrdata_en_last.eq(wrdata_en)
 482         m.d.comb += dq_oe.eq(wrdata_en[cwl_sys_latency + 1] | wrdata_en[cwl_sys_latency + 2])
 483         m.d.comb += bl8_chunk.eq(wrdata_en[cwl_sys_latency + 1])
 484         m.d.comb += dqs_oe.eq(dq_oe | wrdata_en[cwl_sys_latency + 3])
 485
 486         # Write DQS Postamble/Preamble Control Path ------------------------------------------------
 487         # Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
 488         # write. During writes, DQS tristate is configured as output for at least 4 sys_clk cycles:
 489         # 1 for Preamble, 2 for the Write and 1 for the Postamble.
 490         m.d.comb += dqs_preamble.eq(wrdata_en[cwl_sys_latency + 0] & ~wrdata_en[cwl_sys_latency + 1])
 491         m.d.comb += dqs_postamble.eq(wrdata_en[cwl_sys_latency + 4] & ~wrdata_en[cwl_sys_latency + 3])
 492
 493         return m