gram/phy/ecp5ddrphy.py

   1 # This file is Copyright (c) 2019 David Shah <dave@ds0.me>
   2 # This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   4 # License: BSD
   5
   6 # 1:2 frequency-ratio DDR3 PHY for Lattice's ECP5
   7 # DDR3: 800 MT/s
   8
   9 import math
  10
  11 from nmigen import *
  12 from nmigen.lib.cdc import FFSynchronizer
  13 from nmigen.utils import log2_int
  14
  15 from lambdasoc.periph import Peripheral
  16
  17 import gram.stream as stream
  18 from gram.common import *
  19 from gram.phy.dfi import Interface
  20 from gram.compat import Timeline
  21
  22 # Lattice ECP5 DDR PHY Initialization --------------------------------------------------------------
  23
  24
  25 class ECP5DDRPHYInit(Elaboratable):
  26     def __init__(self):
  27         self.pause = Signal()
  28         self.stop = Signal()
  29         self.delay = Signal()
  30         self.reset = Signal()
  31
  32     def elaborate(self, platform):
  33         m = Module()
  34
  35         new_lock = Signal()
  36         update = Signal()
  37         freeze = Signal()
  38
  39         # DDRDLLA instance -------------------------------------------------------------------------
  40         _lock = Signal()
  41         delay = Signal()
  42         m.submodules += Instance("DDRDLLA",
  43                                  i_CLK=ClockSignal("sync2x"),
  44                                  i_RST=ResetSignal("init"),
  45                                  i_UDDCNTLN=~update,
  46                                  i_FREEZE=freeze,
  47                                  o_DDRDEL=delay,
  48                                  o_LOCK=_lock
  49                                  )
  50         lock = Signal()
  51         lock_d = Signal()
  52         m.submodules += FFSynchronizer(_lock, lock, o_domain="init")
  53         m.d.init += lock_d.eq(lock)
  54         m.d.sync += new_lock.eq(lock & ~lock_d)
  55
  56         # DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
  57         t = 8  # in cycles
  58         tl = Timeline([
  59             (1*t,  [freeze.eq(1)]),  # Freeze DDRDLLA
  60             (2*t,  [self.stop.eq(1)]),   # Stop ECLK domain
  61             (3*t,  [self.reset.eq(1)]),  # Reset ECLK domain
  62             (4*t,  [self.reset.eq(0)]),  # Release ECLK domain reset
  63             (5*t,  [self.stop.eq(0)]),   # Release ECLK domain stop
  64             (6*t,  [freeze.eq(0)]),  # Release DDRDLLA freeze
  65             (7*t,  [self.pause.eq(1)]),  # Pause DQSBUFM
  66             (8*t,  [update.eq(1)]),  # Update DDRDLLA
  67             (9*t,  [update.eq(0)]),  # Release DDRDMMA update
  68             (10*t, [self.pause.eq(0)]),  # Release DQSBUFM pause
  69         ])
  70         m.submodules += tl
  71         # Wait DDRDLLA Lock
  72         m.d.comb += tl.trigger.eq(new_lock)
  73
  74         m.d.comb += self.delay.eq(delay)
  75
  76         return m
  77
  78 # Lattice ECP5 DDR PHY -----------------------------------------------------------------------------
  79
  80
  81 class ECP5DDRPHY(Peripheral, Elaboratable):
  82     def __init__(self, pads, sys_clk_freq=100e6):
  83         super().__init__(name="phy")
  84
  85         self.pads = pads
  86         self._sys_clk_freq = sys_clk_freq
  87
  88         databits = len(self.pads.dq.io)
  89         assert databits % 8 == 0
  90
  91         # CSR
  92         bank = self.csr_bank()
  93
  94         self._dly_sel = bank.csr(databits//8, "rw")
  95
  96         self._rdly_dq_rst = bank.csr(1, "rw")
  97         self._rdly_dq_inc = bank.csr(1, "rw")
  98         self._rdly_dq_bitslip_rst = bank.csr(1, "rw")
  99         self._rdly_dq_bitslip = bank.csr(1, "rw")
 100
 101         self._burstdet_clr = bank.csr(1, "rw")
 102         self._burstdet_seen = bank.csr(databits//8, "r")
 103
 104         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
 105         self.bus = self._bridge.bus
 106
 107         addressbits = len(self.pads.a.o0)
 108         bankbits = len(self.pads.ba.o0)
 109         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n.o)
 110         databits = len(self.pads.dq.io)
 111         self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
 112
 113         # PHY settings -----------------------------------------------------------------------------
 114         tck = 2/(2*2*self._sys_clk_freq)
 115         nphases = 2
 116         databits = len(self.pads.dq.io)
 117         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n.o)
 118         cl, cwl = get_cl_cw("DDR3", tck)
 119         cl_sys_latency = get_sys_latency(nphases, cl)
 120         cwl_sys_latency = get_sys_latency(nphases, cwl)
 121         rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
 122         wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
 123         self.settings = PhySettings(
 124             phytype="ECP5DDRPHY",
 125             memtype="DDR3",
 126             databits=databits,
 127             dfi_databits=4*databits,
 128             nranks=nranks,
 129             nphases=nphases,
 130             rdphase=rdphase,
 131             wrphase=wrphase,
 132             rdcmdphase=rdcmdphase,
 133             wrcmdphase=wrcmdphase,
 134             cl=cl,
 135             cwl=cwl,
 136             read_latency=2 + cl_sys_latency + 2 + log2_int(4//nphases) + 4,
 137             write_latency=cwl_sys_latency
 138         )
 139
 140     def elaborate(self, platform):
 141         m = Module()
 142
 143         m.submodules += self._bridge
 144
 145         tck = 2/(2*2*self._sys_clk_freq)
 146         nphases = 2
 147         databits = len(self.pads.dq.io)
 148
 149         # Init -------------------------------------------------------------------------------------
 150         m.submodules.init = init = ECP5DDRPHYInit()
 151
 152         # Parameters -------------------------------------------------------------------------------
 153         cl, cwl = get_cl_cw("DDR3", tck)
 154         cl_sys_latency = get_sys_latency(nphases, cl)
 155         cwl_sys_latency = get_sys_latency(nphases, cwl)
 156
 157         # Observation
 158         self.datavalid = Signal(databits//8)
 159
 160         # DFI Interface ----------------------------------------------------------------------------
 161         dfi = self.dfi
 162
 163         bl8_chunk = Signal()
 164         rddata_en = Signal(self.settings.read_latency)
 165
 166         # Clock --------------------------------------------------------------------------------
 167         m.d.comb += [
 168             self.pads.clk.o_clk.eq(ClockSignal("dramsync")),
 169             self.pads.clk.o_fclk.eq(ClockSignal("sync2x")),
 170         ]
 171         for i in range(len(self.pads.clk.o0)):
 172             m.d.comb += [
 173                 self.pads.clk.o0[i].eq(0),
 174                 self.pads.clk.o1[i].eq(1),
 175                 self.pads.clk.o2[i].eq(0),
 176                 self.pads.clk.o3[i].eq(1),
 177             ]
 178
 179         # Addresses and Commands ---------------------------------------------------------------
 180         m.d.comb += [
 181             self.pads.a.o_clk.eq(ClockSignal("dramsync")),
 182             self.pads.a.o_fclk.eq(ClockSignal("sync2x")),
 183             self.pads.ba.o_clk.eq(ClockSignal("dramsync")),
 184             self.pads.ba.o_fclk.eq(ClockSignal("sync2x")),
 185         ]
 186         for i in range(len(self.pads.a.o0)):
 187             m.d.comb += [
 188                 self.pads.a.o0[i].eq(dfi.phases[0].address[i]),
 189                 self.pads.a.o1[i].eq(dfi.phases[0].address[i]),
 190                 self.pads.a.o2[i].eq(dfi.phases[1].address[i]),
 191                 self.pads.a.o3[i].eq(dfi.phases[1].address[i]),
 192             ]
 193         for i in range(len(self.pads.ba.o0)):
 194             m.d.comb += [
 195                 self.pads.ba.o0[i].eq(dfi.phases[0].bank[i]),
 196                 self.pads.ba.o1[i].eq(dfi.phases[0].bank[i]),
 197                 self.pads.ba.o2[i].eq(dfi.phases[1].bank[i]),
 198                 self.pads.ba.o3[i].eq(dfi.phases[1].bank[i]),
 199             ]
 200
 201         controls = ["ras_n", "cas_n", "we_n", "clk_en", "odt"]
 202         if hasattr(self.pads, "reset_n"):
 203             controls.append("reset_n")
 204         if hasattr(self.pads, "cs_n"):
 205             controls.append("cs_n")
 206         for name in controls:
 207             m.d.comb += [
 208                 getattr(self.pads, name).o_clk.eq(ClockSignal("dramsync")),
 209                 getattr(self.pads, name).o_fclk.eq(ClockSignal("sync2x")),
 210             ]
 211             for i in range(len(getattr(self.pads, name).o0)):
 212                 m.d.comb += [
 213                     getattr(self.pads, name).o0[i].eq(getattr(dfi.phases[0], name)[i]),
 214                     getattr(self.pads, name).o1[i].eq(getattr(dfi.phases[0], name)[i]),
 215                     getattr(self.pads, name).o2[i].eq(getattr(dfi.phases[1], name)[i]),
 216                     getattr(self.pads, name).o3[i].eq(getattr(dfi.phases[1], name)[i]),
 217                 ]
 218
 219         # DQ ---------------------------------------------------------------------------------------
 220         dq_oe = Signal()
 221         dqs_oe = Signal()
 222         dqs_pattern = DQSPattern()
 223         m.submodules += dqs_pattern
 224         for i in range(databits//8):
 225             # DQSBUFM
 226             dqs_i = Signal()
 227             dqsr90 = Signal()
 228             dqsw270 = Signal()
 229             dqsw = Signal()
 230             rdpntr = Signal(3)
 231             wrpntr = Signal(3)
 232             rdly = Signal(7)
 233             with m.If(self._dly_sel.w_data[i]):
 234                 with m.If(self._rdly_dq_rst.w_stb):
 235                     m.d.sync += rdly.eq(0)
 236                 with m.Elif(self._rdly_dq_inc.w_stb):
 237                     m.d.sync += rdly.eq(rdly + 1)
 238             datavalid = Signal()
 239             burstdet = Signal()
 240             dqs_read = Signal()
 241             dqs_bitslip = Signal(2)
 242             with m.If(self._dly_sel.w_data[i]):
 243                 with m.If(self._rdly_dq_bitslip_rst.w_stb):
 244                     m.d.sync += dqs_bitslip.eq(0)
 245                 with m.Elif(self._rdly_dq_bitslip.w_stb):
 246                     m.d.sync += dqs_bitslip.eq(dqs_bitslip + 1)
 247             with m.Switch(dqs_bitslip):
 248                 for j, b in enumerate(range(-2, 2)):
 249                     with m.Case(j):
 250                         m.d.sync += dqs_read.eq(1)
 251
 252             m.submodules += Instance("DQSBUFM",
 253                                      p_DQS_LI_DEL_ADJ="MINUS",
 254                                      p_DQS_LI_DEL_VAL=1,
 255                                      p_DQS_LO_DEL_ADJ="MINUS",
 256                                      p_DQS_LO_DEL_VAL=4,
 257
 258                                      # Delay
 259                                      i_DYNDELAY0=0,
 260                                      i_DYNDELAY1=0,
 261                                      i_DYNDELAY2=0,
 262                                      i_DYNDELAY3=0,
 263                                      i_DYNDELAY4=0,
 264                                      i_DYNDELAY5=0,
 265                                      i_DYNDELAY6=0,
 266                                      i_DYNDELAY7=0,
 267
 268                                      # Clocks / Reset
 269                                      i_SCLK=ClockSignal("sync"),
 270                                      i_ECLK=ClockSignal("sync2x"),
 271                                      i_RST=ResetSignal("dramsync"),
 272                                      i_DDRDEL=init.delay,
 273                                      i_PAUSE=init.pause | self._dly_sel.w_data[i],
 274
 275                                      # Control
 276                                      # Assert LOADNs to use DDRDEL control
 277                                      i_RDLOADN=0,
 278                                      i_RDMOVE=0,
 279                                      i_RDDIRECTION=1,
 280                                      i_WRLOADN=0,
 281                                      i_WRMOVE=0,
 282                                      i_WRDIRECTION=1,
 283
 284                                      # Reads (generate shifted DQS clock for reads)
 285                                      i_READ0=dqs_read,
 286                                      i_READ1=dqs_read,
 287                                      i_READCLKSEL0=rdly[0],
 288                                      i_READCLKSEL1=rdly[1],
 289                                      i_READCLKSEL2=rdly[2],
 290                                      i_DQSI=dqs_i,
 291                                      o_DQSR90=dqsr90,
 292                                      o_RDPNTR0=rdpntr[0],
 293                                      o_RDPNTR1=rdpntr[1],
 294                                      o_RDPNTR2=rdpntr[2],
 295                                      o_WRPNTR0=wrpntr[0],
 296                                      o_WRPNTR1=wrpntr[1],
 297                                      o_WRPNTR2=wrpntr[2],
 298                                      o_DATAVALID=self.datavalid[i],
 299                                      o_BURSTDET=burstdet,
 300
 301                                      # Writes (generate shifted ECLK clock for writes)
 302                                      o_DQSW270=dqsw270,
 303                                      o_DQSW=dqsw
 304                                      )
 305             burstdet_d = Signal()
 306             m.d.sync += burstdet_d.eq(burstdet)
 307             with m.If(self._burstdet_clr.w_stb):
 308                 m.d.sync += self._burstdet_seen.r_data[i].eq(0)
 309             with m.If(burstdet & ~burstdet_d):
 310                 m.d.sync += self._burstdet_seen.r_data[i].eq(1)
 311
 312             # DQS and DM ---------------------------------------------------------------------------
 313             dm_o_data = Signal(8)
 314             dm_o_data_d = Signal(8)
 315             dm_o_data_muxed = Signal(4)
 316             m.d.comb += dm_o_data.eq(Cat(
 317                 dfi.phases[0].wrdata_mask[0*databits//8+i],
 318                 dfi.phases[0].wrdata_mask[1*databits//8+i],
 319                 dfi.phases[0].wrdata_mask[2*databits//8+i],
 320                 dfi.phases[0].wrdata_mask[3*databits//8+i],
 321
 322                 dfi.phases[1].wrdata_mask[0*databits//8+i],
 323                 dfi.phases[1].wrdata_mask[1*databits//8+i],
 324                 dfi.phases[1].wrdata_mask[2*databits//8+i],
 325                 dfi.phases[1].wrdata_mask[3*databits//8+i]),
 326             )
 327             m.d.sync += dm_o_data_d.eq(dm_o_data)
 328             with m.Switch(bl8_chunk):
 329                 with m.Case(0):
 330                     m.d.sync += dm_o_data_muxed.eq(dm_o_data[:4])
 331                 with m.Case(1):
 332                     m.d.sync += dm_o_data_muxed.eq(dm_o_data_d[4:])
 333             m.submodules += Instance("ODDRX2DQA",
 334                                      i_RST=ResetSignal("dramsync"),
 335                                      i_ECLK=ClockSignal("sync2x"),
 336                                      i_SCLK=ClockSignal("dramsync"),
 337                                      i_DQSW270=dqsw270,
 338                                      i_D0=dm_o_data_muxed[0],
 339                                      i_D1=dm_o_data_muxed[1],
 340                                      i_D2=dm_o_data_muxed[2],
 341                                      i_D3=dm_o_data_muxed[3],
 342                                      o_Q=self.pads.dm.o[i]
 343                                      )
 344
 345             dqs = Signal()
 346             dqs_oe_n = Signal()
 347             m.submodules += [
 348                 Instance("ODDRX2DQSB",
 349                          i_RST=ResetSignal("dramsync"),
 350                          i_ECLK=ClockSignal("sync2x"),
 351                          i_SCLK=ClockSignal(),
 352                          i_DQSW=dqsw,
 353                          i_D0=0,  # FIXME: dqs_pattern.o[3],
 354                          i_D1=1,  # FIXME: dqs_pattern.o[2],
 355                          i_D2=0,  # FIXME: dqs_pattern.o[1],
 356                          i_D3=1,  # FIXME: dqs_pattern.o[0],
 357                          o_Q=dqs
 358                          ),
 359                 Instance("TSHX2DQSA",
 360                          i_RST=ResetSignal("dramsync"),
 361                          i_ECLK=ClockSignal("sync2x"),
 362                          i_SCLK=ClockSignal(),
 363                          i_DQSW=dqsw,
 364                          i_T0=~(dqs_pattern.preamble | dqs_oe |
 365                                 dqs_pattern.postamble),
 366                          i_T1=~(dqs_pattern.preamble | dqs_oe |
 367                                 dqs_pattern.postamble),
 368                          o_Q=dqs_oe_n
 369                          ),
 370                 Instance("BB",
 371                     i_I=dqs,
 372                     i_T=dqs_oe_n,
 373                     o_O=dqs_i,
 374                     io_B=self.pads.dqs.io[i]
 375                     )
 376             ]
 377
 378             for j in range(8*i, 8*(i+1)):
 379                 dq_o = Signal()
 380                 dq_i = Signal()
 381                 dq_oe_n = Signal()
 382                 dq_i_delayed = Signal()
 383                 dq_i_data = Signal(8)
 384                 dq_o_data = Signal(8)
 385                 dq_o_data_d = Signal(8)
 386                 dq_o_data_muxed = Signal(4)
 387                 m.d.comb += dq_o_data.eq(Cat(
 388                     dfi.phases[0].wrdata[0*databits+j],
 389                     dfi.phases[0].wrdata[1*databits+j],
 390                     dfi.phases[0].wrdata[2*databits+j],
 391                     dfi.phases[0].wrdata[3*databits+j],
 392
 393                     dfi.phases[1].wrdata[0*databits+j],
 394                     dfi.phases[1].wrdata[1*databits+j],
 395                     dfi.phases[1].wrdata[2*databits+j],
 396                     dfi.phases[1].wrdata[3*databits+j])
 397                 )
 398                 m.d.sync += dq_o_data_d.eq(dq_o_data)
 399                 # FIXME: use self.comb?
 400                 with m.Switch(bl8_chunk):
 401                     with m.Case(0):
 402                         m.d.sync += dq_o_data_muxed.eq(dq_o_data[:4])
 403                     with m.Case(1):
 404                         m.d.sync += dq_o_data_muxed.eq(dq_o_data_d[4:])
 405                 _dq_i_data = Signal(4)
 406                 m.submodules += [
 407                     Instance("ODDRX2DQA",
 408                              i_RST=ResetSignal("dramsync"),
 409                              i_ECLK=ClockSignal("sync2x"),
 410                              i_SCLK=ClockSignal(),
 411                              i_DQSW270=dqsw270,
 412                              i_D0=dq_o_data_muxed[0],
 413                              i_D1=dq_o_data_muxed[1],
 414                              i_D2=dq_o_data_muxed[2],
 415                              i_D3=dq_o_data_muxed[3],
 416                              o_Q=dq_o
 417                              ),
 418                     Instance("DELAYF",
 419                              p_DEL_MODE="DQS_ALIGNED_X2",
 420                              i_LOADN=1,
 421                              i_MOVE=0,
 422                              i_DIRECTION=0,
 423                              i_A=dq_i,
 424                              o_Z=dq_i_delayed
 425                              ),
 426                     Instance("IDDRX2DQA",
 427                              i_RST=ResetSignal("dramsync"),
 428                              i_ECLK=ClockSignal("sync2x"),
 429                              i_SCLK=ClockSignal(),
 430                              i_DQSR90=dqsr90,
 431                              i_RDPNTR0=rdpntr[0],
 432                              i_RDPNTR1=rdpntr[1],
 433                              i_RDPNTR2=rdpntr[2],
 434                              i_WRPNTR0=wrpntr[0],
 435                              i_WRPNTR1=wrpntr[1],
 436                              i_WRPNTR2=wrpntr[2],
 437                              i_D=dq_i_delayed,
 438                              o_Q0=_dq_i_data[0],
 439                              o_Q1=_dq_i_data[1],
 440                              o_Q2=_dq_i_data[2],
 441                              o_Q3=_dq_i_data[3],
 442                              )
 443                 ]
 444                 m.d.sync += dq_i_data[:4].eq(dq_i_data[4:])
 445                 m.d.sync += dq_i_data[4:].eq(_dq_i_data)
 446                 m.d.sync += [
 447                     dfi.phases[0].rddata[0*databits+j].eq(dq_i_data[0]),
 448                     dfi.phases[0].rddata[1*databits+j].eq(dq_i_data[1]),
 449                     dfi.phases[0].rddata[2*databits+j].eq(dq_i_data[2]),
 450                     dfi.phases[0].rddata[3*databits+j].eq(dq_i_data[3]),
 451                     dfi.phases[1].rddata[0*databits+j].eq(dq_i_data[4]),
 452                     dfi.phases[1].rddata[1*databits+j].eq(dq_i_data[5]),
 453                     dfi.phases[1].rddata[2*databits+j].eq(dq_i_data[6]),
 454                     dfi.phases[1].rddata[3*databits+j].eq(dq_i_data[7]),
 455                 ]
 456                 m.submodules += [
 457                     Instance("TSHX2DQA",
 458                              i_RST=ResetSignal("dramsync"),
 459                              i_ECLK=ClockSignal("sync2x"),
 460                              i_SCLK=ClockSignal(),
 461                              i_DQSW270=dqsw270,
 462                              i_T0=~(dqs_pattern.preamble | dq_oe |
 463                                     dqs_pattern.postamble),
 464                              i_T1=~(dqs_pattern.preamble | dq_oe |
 465                                     dqs_pattern.postamble),
 466                              o_Q=dq_oe_n,
 467                              ),
 468                     Instance("BB",
 469                         i_I=dq_o,
 470                         i_T=dq_oe_n,
 471                         o_O=dq_i,
 472                         io_B=self.pads.dq.io[j]
 473                         )
 474                 ]
 475
 476         # Read Control Path ------------------------------------------------------------------------
 477         # Creates a shift register of read commands coming from the DFI interface. This shift register
 478         # is used to control DQS read (internal read pulse of the DQSBUF) and to indicate to the
 479         # DFI interface that the read data is valid.
 480         #
 481         # The DQS read must be asserted for 2 sys_clk cycles before the read data is coming back from
 482         # the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2)
 483         #
 484         # The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI
 485         # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies.
 486         rddata_en_last = Signal.like(rddata_en)
 487         m.d.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last))
 488         m.d.sync += rddata_en_last.eq(rddata_en)
 489         m.d.sync += [phase.rddata_valid.eq(rddata_en[-1])
 490                      for phase in dfi.phases]
 491
 492         # Write Control Path -----------------------------------------------------------------------
 493         # Creates a shift register of write commands coming from the DFI interface. This shift register
 494         # is used to control DQ/DQS tristates and to select write data of the DRAM burst from the DFI
 495         # interface: The PHY is operating in halfrate mode (so provide 4 datas every sys_clk cycles:
 496         # 2x for DDR, 2x for halfrate) but DDR3 requires a burst of 8 datas (BL8) for best efficiency.
 497         # Writes are then performed in 2 sys_clk cycles and data needs to be selected for each cycle.
 498         # FIXME: understand +2
 499         wrdata_en = Signal(cwl_sys_latency + 5)
 500         wrdata_en_last = Signal.like(wrdata_en)
 501         m.d.comb += wrdata_en.eq(
 502             Cat(dfi.phases[self.settings.wrphase].wrdata_en, wrdata_en_last))
 503         m.d.sync += wrdata_en_last.eq(wrdata_en)
 504         m.d.comb += dq_oe.eq(wrdata_en[cwl_sys_latency + 2]
 505                              | wrdata_en[cwl_sys_latency + 3])
 506         m.d.comb += bl8_chunk.eq(wrdata_en[cwl_sys_latency + 1])
 507         m.d.comb += dqs_oe.eq(dq_oe)
 508
 509         # Write DQS Postamble/Preamble Control Path ------------------------------------------------
 510         # Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
 511         # write. During writes, DQS tristate is configured as output for at least 4 sys_clk cycles:
 512         # 1 for Preamble, 2 for the Write and 1 for the Postamble.
 513         m.d.comb += dqs_pattern.preamble.eq(
 514             wrdata_en[cwl_sys_latency + 1] & ~wrdata_en[cwl_sys_latency + 2])
 515         m.d.comb += dqs_pattern.postamble.eq(
 516             wrdata_en[cwl_sys_latency + 4] & ~wrdata_en[cwl_sys_latency + 3])
 517
 518         return m