gram/simulation/.gitignore

   1 # Icarius Verilog generated files
   2 simcrg
   3 simsoc
   4
   5 # nMigen generated files
   6 build/
   7 build_simsoc/
   8 build_simcrg/
   9
  10 # Simulation output
  11 *.vcd
  12 *.fst
  13
  14 # Patched files
  15 DDRDLLA.v