gram/simulation/DDRDLLA.v

   1 // --------------------------------------------------------------------
   2 // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
   3 // --------------------------------------------------------------------
   4 // Copyright (c) 2007 by Lattice Semiconductor Corporation
   5 // --------------------------------------------------------------------
   6 //
   7 //
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  12 //
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  17 //                     email: techsupport@latticesemi.com
  18 //
  19 // --------------------------------------------------------------------
  20 //
  21 // Simulation Library File for DDRDLLA in ECP5U/M, LIFMD
  22 //
  23 // $Header:
  24 //
  25
  26 `celldefine
  27 `timescale 1 ns / 1 ps
  28 module DDRDLLA (CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL7, DCNTL6, DCNTL5, DCNTL4,
  29                 DCNTL3, DCNTL2, DCNTL1, DCNTL0);
  30
  31 parameter FORCE_MAX_DELAY = "NO";
  32 parameter GSR = "ENABLED";
  33
  34 parameter   LOCK_CYC   = 200;
  35
  36 localparam PHASE_SHIFT = 90;
  37 input  CLK, RST, UDDCNTLN, FREEZE;
  38 output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0;
  39
  40 wire RST_int, UDDCNTL_int, UDDCNTL_buf;
  41 reg  LOCK_int, DDRDEL_int;
  42 wire clkin_in, FREEZEB, clkin_out;
  43 reg last_clkin_in, freeze_clk_sync, freeze_clk_sync2n;
  44 reg SRN, clock_valid;
  45 integer cntl_ratio;
  46 wire [7:0] cntl_reg;
  47 reg  [7:0] cntl_reg_final;
  48 reg  [7:0] cntl_reg_update;
  49 realtime next_clock_edge, last_clock_edge;
  50 realtime t_in_clk, t_in_clk1, t_in_clk2;
  51 realtime t_90, t_45, t_57, t_68, t_79;
  52 realtime t_101, t_112, t_123, t_135;
  53 realtime delta;
  54
  55 initial
  56 begin
  57    cntl_reg_update = 8'b000000;
  58    cntl_ratio = 0;
  59    delta = 0.025;
  60    clock_valid = 1'b0;
  61 end
  62
  63 //  tri1 GSR_sig = GSR_INST.GSRNET;
  64 //  tri1 PUR_sig = PUR_INST.PURNET;
  65 tri1 GSR_sig, PUR_sig;
  66 `ifndef mixed_hdl
  67    assign GSR_sig = GSR_INST.GSRNET;
  68    assign PUR_sig = PUR_INST.PURNET;
  69 `else
  70    gsr_pur_assign gsr_pur_assign_inst (GSR_sig, PUR_sig);
  71 `endif
  72
  73 buf buf_clkin (clkin_in, CLK);
  74 buf buf_rst  (RSTB1, RST);
  75 buf buf_uddcntl (UDDCNTL_buf, UDDCNTLN);
  76 buf buf_freeze (FREEZEB, FREEZE);
  77
  78 buf buf_lock (LOCK, LOCK_int);
  79 buf buf_ddrdel (DDRDEL, DDRDEL_int);
  80 buf U4 (DCNTL0, cntl_reg_final[0]);
  81 buf U5 (DCNTL1, cntl_reg_final[1]);
  82 buf U6 (DCNTL2, cntl_reg_final[2]);
  83 buf U7 (DCNTL3, cntl_reg_final[3]);
  84 buf U8 (DCNTL4, cntl_reg_final[4]);
  85 buf U9 (DCNTL5, cntl_reg_final[5]);
  86 buf U10 (DCNTL6, cntl_reg_final[6]);
  87 buf U11 (DCNTL7, cntl_reg_final[7]);
  88
  89 integer clk_rising_edge_count;
  90
  91 assign UDDCNTL_int = ~UDDCNTL_buf;
  92
  93 initial
  94 begin
  95    clk_rising_edge_count = 0;
  96    freeze_clk_sync = 1'b0;
  97    freeze_clk_sync2n = 1'b1;
  98    last_clkin_in = 1'b0;
  99 end
 100
 101   always @ (GSR_sig or PUR_sig ) begin
 102     if (GSR == "ENABLED")
 103       SRN = GSR_sig & PUR_sig ;
 104     else if (GSR == "DISABLED")
 105       SRN = PUR_sig;
 106   end
 107
 108   not (SR, SRN);
 109   or INST1 (RST_int, RSTB1, SR);
 110
 111 always @ (clkin_in)
 112 begin
 113    last_clkin_in <= clkin_in;
 114 end
 115
 116 always @ (clkin_in or RST_int)     // neg edge
 117 begin
 118    if (RST_int == 1'b1)
 119    begin
 120       freeze_clk_sync <= 1'b0;
 121       freeze_clk_sync2n <= 1'b1;
 122    end
 123    else if (clkin_in === 1'b0 && last_clkin_in === 1'b1)
 124    begin
 125          freeze_clk_sync <= FREEZEB;
 126          freeze_clk_sync2n <= ~freeze_clk_sync;
 127    end
 128 end
 129
 130 and INST2 (clkin_out, clkin_in, freeze_clk_sync2n);
 131
 132 always @(posedge clkin_out or posedge RST_int)
 133 begin
 134    if (RST_int)
 135        clk_rising_edge_count = 0;
 136    else
 137        clk_rising_edge_count = clk_rising_edge_count + 1;
 138 end
 139
 140 always @(clk_rising_edge_count or RST_int)
 141 begin
 142     if (RST_int)
 143          LOCK_int = 1'b0;
 144     else if (clk_rising_edge_count > LOCK_CYC)
 145          LOCK_int = 1'b1;
 146 end
 147
 148 always @(LOCK_int or UDDCNTL_int or RST_int)
 149 begin
 150   if (RST_int)
 151       DDRDEL_int = 1'b0;
 152   else if (UDDCNTL_int == 1'b1)
 153       DDRDEL_int = LOCK_int;
 154   else
 155       DDRDEL_int = DDRDEL_int;
 156 end
 157
 158   always @(posedge clkin_in)
 159    begin
 160    last_clock_edge=next_clock_edge;
 161    next_clock_edge=$realtime;
 162
 163     if (last_clock_edge > 0)
 164         begin
 165         t_in_clk <= next_clock_edge - last_clock_edge;
 166         t_in_clk1 <= t_in_clk;
 167         end
 168
 169     if (t_in_clk > 0)
 170         begin
 171          if ( ((t_in_clk - t_in_clk1) < 0.0001) && ((t_in_clk - t_in_clk1) > -0.0001))
 172 //         if (t_in_clk == t_in_clk1)
 173             clock_valid = 1;
 174          else
 175             clock_valid = 0;
 176         end
 177
 178     if (t_in_clk > 0)
 179     begin
 180         t_45 = (t_in_clk / 8 );
 181         t_57 = ((t_in_clk * 5) / 32 );
 182         t_68 = ((t_in_clk * 3) / 16 );
 183         t_79 = ((t_in_clk * 7) / 32 );
 184         t_90 = (t_in_clk / 4 );
 185         t_101 = ((t_in_clk * 9) / 32 );
 186         t_112 = ((t_in_clk * 5) / 16 );
 187         t_123 = ((t_in_clk * 11) / 32 );
 188         t_135 = ((t_in_clk * 3) / 8 );
 189      end
 190
 191      if (PHASE_SHIFT == 90)
 192      begin
 193         if (t_90 > 0)
 194         begin
 195            cntl_ratio = (t_90 / delta);
 196         end
 197      end
 198    end
 199
 200   assign cntl_reg = cntl_ratio;
 201
 202   always @(cntl_reg or UDDCNTL_int or clock_valid)
 203   begin
 204      if (clock_valid == 1'b1)
 205      begin
 206         if (UDDCNTL_int == 1'b1)
 207         begin
 208            cntl_reg_update <= cntl_reg;
 209         end
 210      end
 211   end
 212
 213   always @(RST_int or cntl_reg_update)
 214   begin
 215      if (RST_int == 1'b1)
 216         cntl_reg_final <= 8'b00000000;
 217      else
 218         cntl_reg_final <= cntl_reg_update;
 219   end
 220
 221 /* specify
 222
 223 (CLK => LOCK) =  0:0:0, 0:0:0;
 224 (CLK => DDRDEL) =  0:0:0, 0:0:0;
 225 (RST => LOCK) =  0:0:0, 0:0:0;
 226 (RST => DDRDEL) =  0:0:0, 0:0:0;
 227 (UDDCNTLN => LOCK) =  0:0:0, 0:0:0;
 228 (UDDCNTLN => DDRDEL) =  0:0:0, 0:0:0;
 229
 230 endspecify */
 231
 232 endmodule
 233
 234 `endcelldefine