gram/simulation/crg.py

   1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 from nmigen import *
   4
   5 __ALL__ = ["ECPIX5CRG"]
   6
   7 class PLL(Elaboratable):
   8     def __init__(self, clkin, clksel=Signal(shape=2, reset=2), clkout1=Signal(), clkout2=Signal(), clkout3=Signal(), clkout4=Signal(), lock=Signal(), CLKI_DIV=1, CLKFB_DIV=1, CLK1_DIV=3, CLK2_DIV=4, CLK3_DIV=5, CLK4_DIV=6):
   9         self.clkin = clkin
  10         self.clkout1 = clkout1
  11         self.clkout2 = clkout2
  12         self.clkout3 = clkout3
  13         self.clkout4 = clkout4
  14         self.clksel = clksel
  15         self.lock = lock
  16         self.CLKI_DIV = CLKI_DIV
  17         self.CLKFB_DIV = CLKFB_DIV
  18         self.CLKOP_DIV = CLK1_DIV
  19         self.CLKOS_DIV = CLK2_DIV
  20         self.CLKOS2_DIV = CLK3_DIV
  21         self.CLKOS3_DIV = CLK4_DIV
  22         self.ports = [
  23             self.clkin,
  24             self.clkout1,
  25             self.clkout2,
  26             self.clkout3,
  27             self.clkout4,
  28             self.clksel,
  29             self.lock,
  30         ]
  31
  32     def elaborate(self, platform):
  33         clkfb = Signal()
  34         pll = Instance("EHXPLLL",
  35                        p_CLKOP_FPHASE=0,
  36                        p_CLKOP_CPHASE=1,
  37                        p_OUTDIVIDER_MUXA='DIVA',
  38                        p_CLKOP_ENABLE='ENABLED',
  39                        p_CLKOP_DIV=self.CLKOP_DIV,
  40                        p_CLKOS_DIV=self.CLKOS_DIV,
  41                        p_CLKOS2_DIV=self.CLKOS2_DIV,
  42                        p_CLKOS3_DIV=self.CLKOS3_DIV,
  43                        p_CLKFB_DIV=self.CLKFB_DIV,
  44                        p_CLKI_DIV=self.CLKI_DIV,
  45                        p_FEEDBK_PATH='INT_OP',
  46                        #p_FREQUENCY_PIN_CLKOP='200',
  47                        i_CLKI=self.clkin,
  48                        i_CLKFB=clkfb,
  49                        i_RST=0,
  50                        i_STDBY=0,
  51                        i_PHASESEL0=1,
  52                        i_PHASESEL1=1,
  53                        i_PHASEDIR=0,
  54                        i_PHASESTEP=0,
  55                        i_PHASELOADREG=0,
  56                        i_PLLWAKESYNC=0,
  57                        i_ENCLKOP=1,
  58                        i_ENCLKOS=1,
  59                        i_ENCLKOS2=0,
  60                        i_ENCLKOS3=0,
  61                        o_CLKOP=self.clkout1,
  62                        o_CLKOS=self.clkout2,
  63                        o_CLKOS2=self.clkout3,
  64                        o_CLKOS3=self.clkout4,
  65                        o_LOCK=self.lock,
  66                        )
  67         m = Module()
  68         m.submodules += pll
  69         with m.If(self.clksel == 0):
  70             m.d.comb += clkfb.eq(self.clkout1)
  71         with m.Elif(self.clksel == 1):
  72             m.d.comb += clkfb.eq(self.clkout2)
  73         with m.Elif(self.clksel == 2):
  74             m.d.comb += clkfb.eq(self.clkout3)
  75         with m.Else():
  76             m.d.comb += clkfb.eq(self.clkout4)
  77         return m
  78
  79
  80 class ECPIX5CRG(Elaboratable):
  81     def __init__(self):
  82         ...
  83
  84     def elaborate(self, platform):
  85         m = Module()
  86
  87         # Get 100Mhz from oscillator
  88         clk100 = platform.request("clk100")
  89         cd_rawclk = ClockDomain("rawclk", local=True, reset_less=True)
  90         m.d.comb += cd_rawclk.clk.eq(clk100)
  91         m.domains += cd_rawclk
  92
  93         # Reset
  94         reset = platform.request(platform.default_rst).i
  95         gsr0 = Signal()
  96         gsr1 = Signal()
  97
  98         m.submodules += [
  99             Instance("FD1S3AX", p_GSR="DISABLED", i_CK=ClockSignal("rawclk"), i_D=~reset, o_Q=gsr0),
 100             Instance("FD1S3AX", p_GSR="DISABLED", i_CK=ClockSignal("rawclk"), i_D=gsr0,   o_Q=gsr1),
 101             Instance("SGSR", i_CLK=ClockSignal("rawclk"), i_GSR=gsr1),
 102         ]
 103
 104         # Power-on delay (655us)
 105         podcnt = Signal(16, reset=2**16-1)
 106         pod_done = Signal()
 107         with m.If(podcnt != 0):
 108             m.d.rawclk += podcnt.eq(podcnt-1)
 109         m.d.comb += pod_done.eq(podcnt == 0)
 110
 111         # Generating sync2x (200Mhz) and init (25Mhz) from clk100
 112         cd_sync2x = ClockDomain("sync2x", local=False)
 113         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf", local=True, reset_less=True)
 114         cd_init = ClockDomain("init", local=False)
 115         cd_sync = ClockDomain("sync", local=False)
 116         cd_dramsync = ClockDomain("dramsync", local=False)
 117         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=2, CLK2_DIV=16, CLK3_DIV=4,
 118             clkout1=ClockSignal("sync2x_unbuf"), clkout2=ClockSignal("init"))
 119         m.submodules += Instance("ECLKSYNCB",
 120                 i_ECLKI = ClockSignal("sync2x_unbuf"),
 121                 i_STOP  = 0,
 122                 o_ECLKO = ClockSignal("sync2x"))
 123         m.domains += cd_sync2x_unbuf
 124         m.domains += cd_sync2x
 125         m.domains += cd_init
 126         m.domains += cd_sync
 127         m.domains += cd_dramsync
 128         m.d.comb += ResetSignal("init").eq(~pll.lock|~pod_done)
 129         m.d.comb += ResetSignal("sync").eq(~pll.lock|~pod_done)
 130         m.d.comb += ResetSignal("dramsync").eq(~pll.lock|~pod_done)
 131
 132         # Generating sync (100Mhz) from sync2x
 133
 134         m.submodules += Instance("CLKDIVF",
 135             p_DIV="2.0",
 136             i_ALIGNWD=0,
 137             i_CLKI=ClockSignal("sync2x"),
 138             i_RST=0,
 139             o_CDIVX=ClockSignal("sync"))
 140         m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync"))
 141
 142         return m