gram/simulation/runsimcrg.sh

   1 #!/bin/bash
   2 set -e
   3
   4 LIB_DIR=/usr/local/diamond/3.11_x64/ispfpga/verilog/data/ecp5u
   5
   6 python simcrg.py
   7 if [[ -z "${YOSYS}" ]]; then
   8         yosys simcrg.ys
   9 else
  10         $YOSYS simcrg.ys
  11 fi
  12 cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v
  13 patch DDRDLLA.v < DDRDLLA.patch
  14 iverilog -Wall -g2012 -s simcrgtb -o simcrg simcrgtb.sv build_simcrg/top.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
  15         ${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
  16         ${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v DDRDLLA.v \
  17         ${LIB_DIR}/CLKDIVF.v
  18 vvp -n simcrg -fst-speed