1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
4 from icarusecpix5platform
import IcarusECPIX5Platform
6 from nmigen
.build
import *
8 class Top(Elaboratable
):
10 self
.dramsync
= Signal()
11 self
.dramsync_reset
= Signal()
13 self
.sync2x
= Signal()
15 def elaborate(self
, platform
):
18 m
.submodules
.crg
= crg
= ECPIX5CRG()
21 Resource("clock_conn", 0, Pins("1 2 3 4", conn
=("pmod", 5,), dir="o"), Attrs(IO_TYPE
="LVCMOS33", PULLMODE
="UP")),
23 platform
.add_resources(resources
)
25 clock_conn
= platform
.request("clock_conn", 0)
27 self
.dramsync
.eq(ClockSignal("dramsync")),
28 self
.dramsync_reset
.eq(ResetSignal("dramsync")),
29 self
.sync
.eq(ClockSignal("sync")),
30 self
.sync2x
.eq(ClockSignal("sync2x")),
32 clock_conn
[0].eq(ClockSignal("dramsync")),
33 clock_conn
[1].eq(ResetSignal("dramsync")),
34 clock_conn
[2].eq(ClockSignal("sync")),
35 clock_conn
[3].eq(ClockSignal("sync2x")),
40 if __name__
== "__main__":
42 IcarusECPIX5Platform().build(top
, build_dir
="build_simcrg")