Rework CRG simulation
[gram.git] / gram / simulation / simcrg.ys
1 read_ilang build_simcrg/top.il
2 delete w:$verilog_initial_trigger
3 proc_prune
4 proc_clean
5 proc_init
6 proc_arst
7 proc_dff
8 proc_rmdead
9 proc_mux
10 proc_clean
11 pmuxtree
12 memory_collect
13 extract_fa -v
14 clean
15 opt
16 clean
17 write_verilog -norename build_simcrg/top.v