gram/simulation/simcrgtb.sv

   1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 `timescale 1 ns / 1 ns
   4
   5 module simcrgtb;
   6   // GSR & PUR init requires for Lattice models
   7   GSR GSR_INST (
   8     .GSR(1'b1)
   9   );
  10   PUR PUR_INST (
  11     .PUR (1'b1)
  12   );
  13
  14   reg clkin;
  15
  16   // Generate 100 Mhz clock
  17   always
  18     begin
  19       clkin = 1'b1;
  20       #5;
  21       clkin = 1'b0;
  22       #5;
  23     end
  24
  25   top top (
  26     .clk100_0__io(clkin),
  27     .rst_0__io(1'b0)
  28   );
  29
  30   initial
  31     begin
  32       $dumpfile("simcrg.fst");
  33       $dumpvars(0, top);
  34       #1000000 $finish;
  35     end
  36
  37   initial
  38     begin
  39       assert (top.crg_dramsync_rst == 1'b1) else $error("DRAM clock domain is not reset at t=0");
  40     end
  41
  42   always @(negedge top.crg_dramsync_rst)
  43     begin
  44       assert($time > 600000) else $error("DRAM sync got out of reset before 600us (too early)");
  45       assert($time < 700000) else $error("DRAM sync got out of reset after 700us (too late)");
  46     end
  47
  48   time last_dramsync_tick;
  49   always @(posedge top.crg_dramsync_clk)
  50     begin
  51       if (top.crg_dramsync_rst == 1'b0)
  52         begin
  53           assert ($time - last_dramsync_tick == 10) else $error("dramsync isn't running at 100Mhz");
  54         end
  55
  56       last_dramsync_tick = $time;
  57     end
  58
  59   time last_sync2x_tick;
  60   always @(posedge top.crg_sync2x_clk)
  61     begin
  62       if (top.crg_dramsync_rst == 1'b0)
  63         begin
  64           assert ($time - last_sync2x_tick == 5) else $error("sync2x isn't running at 200Mhz");
  65         end
  66
  67       last_sync2x_tick = $time;
  68     end
  69 endmodule