gram/simulation/simcrgtb.v

   1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 `timescale 1 ns / 1 ns
   4
   5 module top;
   6   // GSR & PUR init requires for Lattice models
   7   GSR GSR_INST (
   8     .GSR(1'b0)
   9   );
  10   PUR PUR_INST (
  11     .PUR (1'b0)
  12   );
  13
  14   reg clkin;
  15   wire sync;
  16   wire sync2x;
  17   wire dramsync;
  18   wire init;
  19
  20   // Generate 100 Mhz clock
  21   always
  22   begin
  23     clkin = 1'b1;
  24     #5;
  25     clkin = 1'b0;
  26     #5;
  27   end
  28
  29   simcrgtop simcrgtop (
  30     .clkin(clkin),
  31     .sync(sync),
  32     .sync2x(sync2x),
  33     .dramsync(dramsync),
  34     .init(init)
  35   );
  36
  37   initial
  38   begin
  39     $dumpfile("simcrg.vcd");
  40     $dumpvars(0, clkin);
  41     $dumpvars(0, sync);
  42     $dumpvars(0, sync2x);
  43     $dumpvars(0, dramsync);
  44     $dumpvars(0, init);
  45     $dumpvars(0, simcrgtop);
  46
  47     #10000 $finish;
  48   end
  49 endmodule