gram/simulation/simsoctb.v

   1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 `timescale 1 ns / 1 ps
   4
   5 module simsoctb;
   6   // GSR & PUR init requires for Lattice models
   7   GSR GSR_INST (
   8     .GSR(1'b1)
   9   );
  10   PUR PUR_INST (
  11     .PUR (1'b1)
  12   );
  13
  14   reg clkin;
  15   wire sync;
  16   wire sync2x;
  17   wire dramsync;
  18   wire init;
  19
  20   // Generate 100 Mhz clock
  21   always
  22   begin
  23     clkin = 1'b1;
  24     #5;
  25     clkin = 1'b0;
  26     #5;
  27   end
  28
  29   // UART
  30   wire uart_rx;
  31   wire uart_tx;
  32
  33   // DDR3 init
  34   wire dram_ck;
  35   wire dram_cke;
  36   wire dram_we_n;
  37   wire dram_ras_n;
  38   wire dram_cas_n;
  39   wire [15:0] dram_dq;
  40   wire [1:0] dram_dqs;
  41   wire [1:0] dram_dqs_n;
  42   wire [13:0] dram_a;
  43   wire [2:0] dram_ba;
  44   wire [1:0] dram_dm;
  45   wire dram_odt;
  46   wire [1:0] dram_tdqs_n;
  47
  48   ddr3 ram_chip (
  49     .rst_n(1'b1),
  50     .ck(dram_ck),
  51     .ck_n(1'b0),
  52     .cke(dram_cke),
  53     .cs_n(1'b0),
  54     .ras_n(dram_ras_n),
  55     .cas_n(dram_cas_n),
  56     .we_n(dram_we_n),
  57     .dm_tdqs(dram_dm),
  58     .ba(dram_ba),
  59     .addr(dram_a),
  60     .dq(dram_dq),
  61     .dqs(dram_dqs),
  62     .dqs_n(dram_dqs_n),
  63     .tdqs_n(dram_tdqs_n),
  64     .odt(dram_odt)
  65   );
  66
  67   top simsoctop (
  68     .ddr3_0__dq__io(dram_dq),
  69     .ddr3_0__dqs__io(dram_dqs),
  70     .ddr3_0__clk__io(dram_ck),
  71     .ddr3_0__cke__io(dram_cke),
  72     .ddr3_0__we_n__io(dram_we_n),
  73     .ddr3_0__ras_n__io(dram_ras_n),
  74     .ddr3_0__cas_n__io(dram_cas_n),
  75     .ddr3_0__a__io(dram_a),
  76     .ddr3_0__ba__io(dram_ba),
  77     .ddr3_0__dm__io(dram_dm),
  78     .ddr3_0__odt__io(dram_odt),
  79     .clk100_0__io(clkin),
  80     .rst_0__io(1'b0),
  81     .uart_0__rx__io(uart_rx),
  82     .uart_0__tx__io(uart_tx)
  83   );
  84
  85   assign uart_rx = 1'b1;
  86
  87   initial
  88   begin
  89     $dumpfile("simsoc.fst");
  90     $dumpvars(0, clkin);
  91     $dumpvars(0, dram_dq);
  92     $dumpvars(0, dram_dqs);
  93     $dumpvars(0, dram_ck);
  94     $dumpvars(0, dram_cke);
  95     $dumpvars(0, dram_we_n);
  96     $dumpvars(0, dram_ras_n);
  97     $dumpvars(0, dram_cas_n);
  98     $dumpvars(0, dram_a);
  99     $dumpvars(0, dram_ba);
 100     $dumpvars(0, dram_dm);
 101     $dumpvars(0, dram_odt);
 102     $dumpvars(0, uart_rx);
 103     $dumpvars(0, uart_tx);
 104     $dumpvars(0, simsoctop);
 105
 106     // Wait for power-on reset
 107     //#700000; // 700us
 108     #70000;
 109
 110     $finish;
 111   end
 112 endmodule