gram/simulation/simsoctb.v

   1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 `timescale 1 ns / 1 ns
   4
   5 module simsoctb;
   6   //parameter simticks = 70000;
   7   parameter simticks = 4000000;
   8
   9   // GSR & PUR init requires for Lattice models
  10   GSR GSR_INST (
  11     .GSR(1'b1)
  12   );
  13   PUR PUR_INST (
  14     .PUR (1'b1)
  15   );
  16
  17   reg clkin;
  18   wire sync;
  19   wire sync2x;
  20   wire dramsync;
  21   wire init;
  22
  23   // Generate 100 Mhz clock
  24   always
  25   begin
  26     clkin = 1'b1;
  27     #5;
  28     clkin = 1'b0;
  29     #5;
  30   end
  31
  32   // UART
  33   reg uart_rx;
  34   wire uart_tx;
  35
  36   // DDR3 init
  37   wire dram_ck;
  38   wire dram_cke;
  39   wire dram_we_n;
  40   wire dram_ras_n;
  41   wire dram_cas_n;
  42   wire [15:0] dram_dq;
  43   wire [1:0] dram_dqs;
  44   wire [1:0] dram_dqs_n;
  45   wire [13:0] dram_a;
  46   wire [2:0] dram_ba;
  47   wire [1:0] dram_dm;
  48   wire dram_odt;
  49   wire [1:0] dram_tdqs_n;
  50
  51   ddr3 ram_chip (
  52     .rst_n(1'b1),
  53     .ck(dram_ck),
  54     .ck_n(1'b0),
  55     .cke(dram_cke),
  56     .cs_n(1'b0),
  57     .ras_n(dram_ras_n),
  58     .cas_n(dram_cas_n),
  59     .we_n(dram_we_n),
  60     .dm_tdqs(dram_dm),
  61     .ba(dram_ba),
  62     .addr(dram_a),
  63     .dq(dram_dq),
  64     .dqs(dram_dqs),
  65     .dqs_n(dram_dqs_n),
  66     .tdqs_n(dram_tdqs_n),
  67     .odt(dram_odt)
  68   );
  69
  70   top simsoctop (
  71     .ddr3_0__dq__io(dram_dq),
  72     .ddr3_0__dqs__io(dram_dqs),
  73     .ddr3_0__clk__io(dram_ck),
  74     .ddr3_0__cke__io(dram_cke),
  75     .ddr3_0__we_n__io(dram_we_n),
  76     .ddr3_0__ras_n__io(dram_ras_n),
  77     .ddr3_0__cas_n__io(dram_cas_n),
  78     .ddr3_0__a__io(dram_a),
  79     .ddr3_0__ba__io(dram_ba),
  80     .ddr3_0__dm__io(dram_dm),
  81     .ddr3_0__odt__io(dram_odt),
  82     .clk100_0__io(clkin),
  83     .rst_0__io(1'b0),
  84     .uart_0__rx__io(uart_rx),
  85     .uart_0__tx__io(uart_tx)
  86   );
  87
  88   initial
  89     begin
  90       $dumpfile("simsoc.fst");
  91       $dumpvars(0, clkin);
  92       $dumpvars(0, dram_dq);
  93       $dumpvars(0, dram_dqs);
  94       $dumpvars(0, dram_ck);
  95       $dumpvars(0, dram_cke);
  96       $dumpvars(0, dram_we_n);
  97       $dumpvars(0, dram_ras_n);
  98       $dumpvars(0, dram_cas_n);
  99       $dumpvars(0, dram_a);
 100       $dumpvars(0, dram_ba);
 101       $dumpvars(0, dram_dm);
 102       $dumpvars(0, dram_odt);
 103       $dumpvars(0, uart_rx);
 104       $dumpvars(0, uart_tx);
 105       $dumpvars(0, simsoctop);
 106
 107       #simticks $finish;
 108     end
 109
 110   // UART
 111   reg [31:0] tmp;
 112   initial
 113     begin
 114       uart_rx <= 1'b1;
 115       #700000; // POR is ~700us
 116
 117       // Software control
 118       wishbone_write(32'h00009000, 8'h0E); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
 119
 120       wishbone_write(32'h0000900c, 32'h0); // p0 address
 121       wishbone_write(32'h00009010, 32'h0); // p0 baddress
 122       wishbone_write(32'h00009000, 8'h0C); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N
 123       #500000;
 124       wishbone_write(32'h00009000, 8'h0E); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
 125       #500000;
 126
 127       // Set MR2
 128       wishbone_write(32'h0000900c, 32'h200); // p0 address
 129       wishbone_write(32'h00009010, 32'h2); // p0 baddress
 130       wishbone_write(32'h00009004, 8'h0F); // RAS|CAS|WE|CS
 131     end
 132
 133   task wishbone_write;
 134     input [31:0] address;
 135     input [31:0] value;
 136
 137     begin
 138       uart_send(8'h01); // Write command
 139       uart_send(8'h01); // Length
 140       uart_send(address[31:24]); // Address
 141       uart_send(address[23:16]);
 142       uart_send(address[15:8]);
 143       uart_send(address[7:0]);
 144       uart_send(value[31:24]);
 145       uart_send(value[23:16]);
 146       uart_send(value[15:8]);
 147       uart_send(value[7:0]);
 148     end
 149   endtask
 150
 151   task wishbone_read;
 152     input [31:0] address;
 153     output [31:0] value;
 154
 155     begin
 156       uart_send(8'h02); // Read command
 157       uart_send(8'h01); // Length
 158       uart_send(address[31:24]); // Address
 159       uart_send(address[23:16]);
 160       uart_send(address[15:8]);
 161       uart_send(address[7:0]);
 162       uart_read(value[31:24]);
 163       uart_read(value[23:16]);
 164       uart_read(value[15:8]);
 165       uart_read(value[7:0]);
 166     end
 167   endtask
 168
 169   task uart_send;
 170     input [7:0] data;
 171     integer i;
 172
 173     begin
 174       uart_rx <= 1'b0;
 175       #8680;
 176       for (i = 0; i < 8; i = i + 1)
 177         begin
 178           uart_rx <= data[i];
 179           #8680;
 180         end
 181       uart_rx <= 1'b1;
 182       #8680;
 183     end
 184   endtask
 185
 186   task uart_read;
 187     output [7:0] data;
 188     integer i;
 189
 190     begin
 191       while (uart_tx)
 192         begin
 193           #1;
 194         end
 195
 196       for (i = 0; i < 8; i = i+1)
 197         begin
 198           #8680 data[i] <= uart_tx;
 199         end
 200
 201       #8680;
 202     end
 203   endtask
 204 endmodule