Add Wishbone interaction code
[gram.git] / gram / simulation / simsoctb.v
1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
2
3 `timescale 1 ns / 100 ps
4
5 module simsoctb;
6 //parameter simticks = 70000;
7 parameter simticks = 2000000;
8
9 // GSR & PUR init requires for Lattice models
10 GSR GSR_INST (
11 .GSR(1'b1)
12 );
13 PUR PUR_INST (
14 .PUR (1'b1)
15 );
16
17 reg clkin;
18 wire sync;
19 wire sync2x;
20 wire dramsync;
21 wire init;
22
23 // Generate 100 Mhz clock
24 always
25 begin
26 clkin = 1'b1;
27 #5;
28 clkin = 1'b0;
29 #5;
30 end
31
32 // UART
33 reg uart_rx;
34 wire uart_tx;
35
36 // DDR3 init
37 wire dram_ck;
38 wire dram_cke;
39 wire dram_we_n;
40 wire dram_ras_n;
41 wire dram_cas_n;
42 wire [15:0] dram_dq;
43 wire [1:0] dram_dqs;
44 wire [1:0] dram_dqs_n;
45 wire [13:0] dram_a;
46 wire [2:0] dram_ba;
47 wire [1:0] dram_dm;
48 wire dram_odt;
49 wire [1:0] dram_tdqs_n;
50
51 ddr3 ram_chip (
52 .rst_n(1'b1),
53 .ck(dram_ck),
54 .ck_n(1'b0),
55 .cke(dram_cke),
56 .cs_n(1'b0),
57 .ras_n(dram_ras_n),
58 .cas_n(dram_cas_n),
59 .we_n(dram_we_n),
60 .dm_tdqs(dram_dm),
61 .ba(dram_ba),
62 .addr(dram_a),
63 .dq(dram_dq),
64 .dqs(dram_dqs),
65 .dqs_n(dram_dqs_n),
66 .tdqs_n(dram_tdqs_n),
67 .odt(dram_odt)
68 );
69
70 top simsoctop (
71 .ddr3_0__dq__io(dram_dq),
72 .ddr3_0__dqs__io(dram_dqs),
73 .ddr3_0__clk__io(dram_ck),
74 .ddr3_0__cke__io(dram_cke),
75 .ddr3_0__we_n__io(dram_we_n),
76 .ddr3_0__ras_n__io(dram_ras_n),
77 .ddr3_0__cas_n__io(dram_cas_n),
78 .ddr3_0__a__io(dram_a),
79 .ddr3_0__ba__io(dram_ba),
80 .ddr3_0__dm__io(dram_dm),
81 .ddr3_0__odt__io(dram_odt),
82 .clk100_0__io(clkin),
83 .rst_0__io(1'b0),
84 .uart_0__rx__io(uart_rx),
85 .uart_0__tx__io(uart_tx)
86 );
87
88 initial
89 begin
90 $dumpfile("simsoc.fst");
91 $dumpvars(0, clkin);
92 $dumpvars(0, dram_dq);
93 $dumpvars(0, dram_dqs);
94 $dumpvars(0, dram_ck);
95 $dumpvars(0, dram_cke);
96 $dumpvars(0, dram_we_n);
97 $dumpvars(0, dram_ras_n);
98 $dumpvars(0, dram_cas_n);
99 $dumpvars(0, dram_a);
100 $dumpvars(0, dram_ba);
101 $dumpvars(0, dram_dm);
102 $dumpvars(0, dram_odt);
103 $dumpvars(0, uart_rx);
104 $dumpvars(0, uart_tx);
105 $dumpvars(0, simsoctop);
106
107 #simticks $finish;
108 end
109
110 // UART
111 initial
112 begin
113 uart_rx <= 1'b1;
114 #700000; // POR is ~700us
115 wishbone_write(32'hFEEDBACC, 32'hFACE2BED);
116 end
117
118 task wishbone_write;
119 input [31:0] address;
120 input [31:0] value;
121
122 begin
123 uart_send(8'h01); // Write command
124 uart_send(8'h01); // Length
125 uart_send(address[31:24]); // Address
126 uart_send(address[23:16]);
127 uart_send(address[15:8]);
128 uart_send(address[7:0]);
129 uart_send(value[31:24]);
130 uart_send(value[23:16]);
131 uart_send(value[15:8]);
132 uart_send(value[7:0]);
133 end
134 endtask
135
136 task uart_send;
137 input [7:0] data;
138 integer i;
139
140 begin
141 uart_rx <= 1'b0;
142 #8680;
143 for (i = 0; i < 8; i = i + 1)
144 begin
145 uart_rx <= data[i];
146 #8680;
147 end
148 uart_rx <= 1'b1;
149 #8680;
150 end
151 endtask
152 endmodule