1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
3 `timescale 1 ns / 100 ps
6 //parameter simticks = 70000;
7 parameter simticks = 2000000;
9 // GSR & PUR init requires for Lattice models
23 // Generate 100 Mhz clock
44 wire [1:0] dram_dqs_n;
49 wire [1:0] dram_tdqs_n;
71 .ddr3_0__dq__io(dram_dq),
72 .ddr3_0__dqs__io(dram_dqs),
73 .ddr3_0__clk__io(dram_ck),
74 .ddr3_0__cke__io(dram_cke),
75 .ddr3_0__we_n__io(dram_we_n),
76 .ddr3_0__ras_n__io(dram_ras_n),
77 .ddr3_0__cas_n__io(dram_cas_n),
78 .ddr3_0__a__io(dram_a),
79 .ddr3_0__ba__io(dram_ba),
80 .ddr3_0__dm__io(dram_dm),
81 .ddr3_0__odt__io(dram_odt),
84 .uart_0__rx__io(uart_rx),
85 .uart_0__tx__io(uart_tx)
90 $dumpfile("simsoc.fst");
92 $dumpvars(0, dram_dq);
93 $dumpvars(0, dram_dqs);
94 $dumpvars(0, dram_ck);
95 $dumpvars(0, dram_cke);
96 $dumpvars(0, dram_we_n);
97 $dumpvars(0, dram_ras_n);
98 $dumpvars(0, dram_cas_n);
100 $dumpvars(0, dram_ba);
101 $dumpvars(0, dram_dm);
102 $dumpvars(0, dram_odt);
103 $dumpvars(0, uart_rx);
104 $dumpvars(0, uart_tx);
105 $dumpvars(0, simsoctop);
114 #700000; // POR is ~700us
115 wishbone_write(32'hFEEDBACC, 32'hFACE2BED);
119 input [31:0] address;
123 uart_send(8'h01); // Write command
124 uart_send(8'h01); // Length
125 uart_send(address[31:24]); // Address
126 uart_send(address[23:16]);
127 uart_send(address[15:8]);
128 uart_send(address[7:0]);
129 uart_send(value[31:24]);
130 uart_send(value[23:16]);
131 uart_send(value[15:8]);
132 uart_send(value[7:0]);
143 for (i = 0; i < 8; i = i + 1)