1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
6 // GSR & PUR init requires for Lattice models
20 // Generate 100 Mhz clock
41 wire [1:0] dram_dqs_n;
46 wire [1:0] dram_tdqs_n;
68 .ddr3_0__dq__io(dram_dq),
69 .ddr3_0__dqs__io(dram_dqs),
70 .ddr3_0__clk__io(dram_ck),
71 .ddr3_0__cke__io(dram_cke),
72 .ddr3_0__we_n__io(dram_we_n),
73 .ddr3_0__ras_n__io(dram_ras_n),
74 .ddr3_0__cas_n__io(dram_cas_n),
75 .ddr3_0__a__io(dram_a),
76 .ddr3_0__ba__io(dram_ba),
77 .ddr3_0__dm__io(dram_dm),
78 .ddr3_0__odt__io(dram_odt),
81 .uart_0__rx__io(uart_rx),
82 .uart_0__tx__io(uart_tx)
85 assign uart_rx = 1'b1;
89 $dumpfile("simsoc.fst");
91 $dumpvars(0, dram_dq);
92 $dumpvars(0, dram_dqs);
93 $dumpvars(0, dram_ck);
94 $dumpvars(0, dram_cke);
95 $dumpvars(0, dram_we_n);
96 $dumpvars(0, dram_ras_n);
97 $dumpvars(0, dram_cas_n);
99 $dumpvars(0, dram_ba);
100 $dumpvars(0, dram_dm);
101 $dumpvars(0, dram_odt);
102 $dumpvars(0, uart_rx);
103 $dumpvars(0, uart_tx);
104 $dumpvars(0, simsoctop);
106 // Wait for power-on reset