1 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
6 //parameter simticks = 70000;
7 parameter simticks = 60000000;
9 // GSR & PUR init requires for Lattice models
23 // Generate 100 Mhz clock
44 wire [1:0] dram_dqs_n;
49 wire [1:0] dram_tdqs_n;
71 .ddr3_0__dq__io(dram_dq),
72 .ddr3_0__dqs__io(dram_dqs),
73 .ddr3_0__clk__io(dram_ck),
74 .ddr3_0__cke__io(dram_cke),
75 .ddr3_0__we_n__io(dram_we_n),
76 .ddr3_0__ras_n__io(dram_ras_n),
77 .ddr3_0__cas_n__io(dram_cas_n),
78 .ddr3_0__a__io(dram_a),
79 .ddr3_0__ba__io(dram_ba),
80 .ddr3_0__dm__io(dram_dm),
81 .ddr3_0__odt__io(dram_odt),
84 .uart_0__rx__io(uart_rx),
85 .uart_0__tx__io(uart_tx)
90 $dumpfile("simsoc.fst");
92 $dumpvars(0, dram_dq);
93 $dumpvars(0, dram_dqs);
94 $dumpvars(0, dram_ck);
95 $dumpvars(0, dram_cke);
96 $dumpvars(0, dram_we_n);
97 $dumpvars(0, dram_ras_n);
98 $dumpvars(0, dram_cas_n);
100 $dumpvars(0, dram_ba);
101 $dumpvars(0, dram_dm);
102 $dumpvars(0, dram_odt);
103 $dumpvars(0, uart_rx);
104 $dumpvars(0, uart_tx);
105 $dumpvars(0, simsoctop);
115 #700000; // POR is ~700us
118 wishbone_write(32'h00009000 >> 2, 8'h0E); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
120 wishbone_write(32'h0000900c >> 2, 32'h0); // p0 address
121 wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
122 wishbone_write(32'h00009000 >> 2, 8'h0C); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N
124 wishbone_write(32'h00009000 >> 2, 8'h0E); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
128 wishbone_write(32'h0000900c >> 2, 32'h200); // p0 address
129 wishbone_write(32'h00009010 >> 2, 32'h2); // p0 baddress
130 wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
131 wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
134 wishbone_write(32'h0000900c >> 2, 32'h0); // p0 address
135 wishbone_write(32'h00009010 >> 2, 32'h3); // p0 baddress
136 wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
137 wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
140 wishbone_write(32'h0000900c >> 2, 32'h6); // p0 address
141 wishbone_write(32'h00009010 >> 2, 32'h1); // p0 baddress
142 wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
143 wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
146 wishbone_write(32'h0000900c >> 2, 32'h320); // p0 address
147 wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
148 wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
149 wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
153 wishbone_write(32'h0000900c >> 2, 32'h400); // p0 address
154 wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
155 wishbone_write(32'h00009004 >> 2, 8'h03); // WE|CS
159 wishbone_write(32'h00009000 >> 2, 8'h01); // DFII_CONTROL_SEL
162 wishbone_read(32'h10000000 >> 2, tmp);
166 input [31:0] address;
170 uart_send(8'h01); // Write command
171 uart_send(8'h01); // Length
172 uart_send(address[31:24]); // Address
173 uart_send(address[23:16]);
174 uart_send(address[15:8]);
175 uart_send(address[7:0]);
176 uart_send(value[31:24]);
177 uart_send(value[23:16]);
178 uart_send(value[15:8]);
179 uart_send(value[7:0]);
184 input [31:0] address;
188 uart_send(8'h02); // Read command
189 uart_send(8'h01); // Length
190 uart_send(address[31:24]); // Address
191 uart_send(address[23:16]);
192 uart_send(address[15:8]);
193 uart_send(address[7:0]);
194 uart_read(value[31:24]);
195 uart_read(value[23:16]);
196 uart_read(value[15:8]);
197 uart_read(value[7:0]);
208 for (i = 0; i < 8; i = i + 1)
228 for (i = 0; i < 8; i = i+1)
230 #8680 data[i] <= uart_tx;