gram/test/test_common.py

   1 from nmigen import *
   2 from nmigen.hdl.ast import Past
   3
   4 from gram.common import DQSPattern
   5 from utils import *
   6
   7 class DQSPatternTestCase(FHDLTestCase):
   8     def test_async(self):
   9         m = Module()
  10         m.d.sync += Signal().eq(0) # Workaround for nMigen#417
  11         m.submodules.dut = dut = DQSPattern(register=False)
  12
  13         def process():
  14             yield dut.preamble.eq(1) # Preamble=1, Postamble=0
  15             yield
  16             self.assertEqual((yield dut.o), 0b00010101)
  17
  18             yield dut.postamble.eq(1) # Preamble=1, Postamble=1
  19             yield
  20             self.assertEqual((yield dut.o), 0b00010101)
  21
  22             yield dut.preamble.eq(0) # Preamble=0, Postamble=1
  23             yield
  24             self.assertEqual((yield dut.o), 0b01010100)
  25
  26             yield dut.postamble.eq(0) # Preamble=1, Postamble=1
  27             yield
  28             self.assertEqual((yield dut.o), 0b01010101)
  29
  30         runSimulation(m, process, "test_dqspattern_async.vcd")