2 from nmigen
.hdl
.ast
import Past
3 from nmigen
.asserts
import Assert
, Assume
5 from gram
.compat
import *
8 class DelayedEnterTestCase(FHDLTestCase
):
9 def test_sequence(self
):
10 def sequence(expected_delay
):
17 with m
.State("Before-Delayed-Enter"):
18 m
.d
.comb
+= before
.eq(1)
19 m
.next
= "Delayed-Enter"
21 delayed_enter(m
, "Delayed-Enter", "End-Delayed-Enter", expected_delay
)
23 with m
.State("End-Delayed-Enter"):
31 while not (yield end
):
35 self
.assertEqual(delay
, expected_delay
)
37 runSimulation(m
, process
, "test_delayedenter.vcd")
39 with self
.assertRaises(AssertionError):
47 class TimelineTestCase(FHDLTestCase
):
48 def test_sequence(self
):
60 m
.submodules
.timeline
= timeline
63 # Test default value for unset signals
64 self
.assertFalse((yield sigA
))
65 self
.assertFalse((yield sigB
))
67 # Ensure that the sequence isn't triggered without the trigger signal
70 self
.assertFalse((yield sigA
))
71 self
.assertFalse((yield sigB
))
73 yield timeline
.trigger
.eq(1)
75 yield timeline
.trigger
.eq(0)
81 self
.assertTrue((yield sigA
))
82 self
.assertFalse((yield sigB
))
84 self
.assertTrue((yield sigA
))
85 self
.assertFalse((yield sigB
))
87 self
.assertFalse((yield sigA
))
88 self
.assertFalse((yield sigB
))
90 self
.assertFalse((yield sigA
))
91 self
.assertTrue((yield sigB
))
93 self
.assertFalse((yield sigA
))
94 self
.assertFalse((yield sigB
))
96 # Ensure no changes happen once the sequence is done
99 self
.assertFalse((yield sigA
))
100 self
.assertFalse((yield sigB
))
102 runSimulation(m
, process
, "test_timeline.vcd")
104 class RoundRobinOutputMatchSpec(Elaboratable
):
105 def __init__(self
, dut
):
108 def elaborate(self
, platform
):
111 m
.d
.comb
+= Assume(Rose(self
.dut
.stb
).implies(self
.dut
.request
== Past(self
.dut
.request
)))
113 m
.d
.sync
+= Assert(((Past(self
.dut
.request
) != 0) & Past(self
.dut
.stb
)).implies(Past(self
.dut
.request
) & (1 << self
.dut
.grant
)))
117 class RoundRobinTestCase(FHDLTestCase
):
118 def test_sequence(self
):
120 m
.submodules
.rb
= roundrobin
= RoundRobin(8)
123 yield roundrobin
.request
.eq(0b10001000)
124 yield roundrobin
.stb
.eq(1)
128 self
.assertEqual((yield roundrobin
.grant
), 3)
131 self
.assertEqual((yield roundrobin
.grant
), 7)
134 self
.assertEqual((yield roundrobin
.grant
), 3)
135 yield roundrobin
.request
.eq(0b00000001)
139 self
.assertEqual((yield roundrobin
.grant
), 0)
141 runSimulation(m
, process
, "test_roundrobin.vcd")
143 # def test_output_match(self):
144 # roundrobin = RoundRobin(32)
145 # spec = RoundRobinOutputMatchSpec(roundrobin)
146 # self.assertFormal(spec, mode="bmc", depth=10)