gram/test/test_compat.py

   1 #nmigen: UnusedElaboratable=no
   2 from nmigen import *
   3 from nmigen.hdl.ast import Past
   4 from nmigen.asserts import Assert, Assume
   5
   6 from gram.compat import *
   7 from utils import *
   8
   9 class DelayedEnterTestCase(FHDLTestCase):
  10     def test_sequence(self):
  11         def sequence(expected_delay):
  12             m = Module()
  13
  14             before = Signal()
  15             end = Signal()
  16
  17             with m.FSM():
  18                 with m.State("Before-Delayed-Enter"):
  19                     m.d.comb += before.eq(1)
  20                     m.next = "Delayed-Enter"
  21
  22                 delayed_enter(m, "Delayed-Enter", "End-Delayed-Enter", expected_delay)
  23
  24                 with m.State("End-Delayed-Enter"):
  25                     m.d.comb += end.eq(1)
  26
  27             def process():
  28                 while (yield before):
  29                     yield
  30
  31                 delay = 0
  32                 while not (yield end):
  33                     yield
  34                     delay += 1
  35
  36                 self.assertEqual(delay, expected_delay)
  37
  38             runSimulation(m, process, "test_delayedenter.vcd")
  39
  40         with self.assertRaises(AssertionError):
  41             sequence(0)
  42         sequence(1)
  43         sequence(2)
  44         sequence(10)
  45         sequence(100)
  46         sequence(1000)
  47
  48 class TimelineTestCase(FHDLTestCase):
  49     def test_sequence(self):
  50         sigA = Signal()
  51         sigB = Signal()
  52         sigC = Signal()
  53         timeline = Timeline([
  54             (1, sigA.eq(1)),
  55             (5, sigA.eq(1)),
  56             (7, sigA.eq(0)),
  57             (10, sigB.eq(1)),
  58             (11, sigB.eq(0)),
  59         ])
  60         m = Module()
  61         m.submodules.timeline = timeline
  62
  63         def process():
  64             # Test default value for unset signals
  65             self.assertFalse((yield sigA))
  66             self.assertFalse((yield sigB))
  67
  68             # Ensure that the sequence isn't triggered without the trigger signal
  69             for i in range(100):
  70                 yield
  71                 self.assertFalse((yield sigA))
  72                 self.assertFalse((yield sigB))
  73
  74             yield timeline.trigger.eq(1)
  75             yield
  76             yield timeline.trigger.eq(0)
  77
  78             for i in range(11+1):
  79                 yield
  80
  81                 if i == 1:
  82                     self.assertTrue((yield sigA))
  83                     self.assertFalse((yield sigB))
  84                 elif i == 5:
  85                     self.assertTrue((yield sigA))
  86                     self.assertFalse((yield sigB))
  87                 elif i == 7:
  88                     self.assertFalse((yield sigA))
  89                     self.assertFalse((yield sigB))
  90                 elif i == 10:
  91                     self.assertFalse((yield sigA))
  92                     self.assertTrue((yield sigB))
  93                 elif i == 11:
  94                     self.assertFalse((yield sigA))
  95                     self.assertFalse((yield sigB))
  96
  97             # Ensure no changes happen once the sequence is done
  98             for i in range(100):
  99                 yield
 100                 self.assertFalse((yield sigA))
 101                 self.assertFalse((yield sigB))
 102
 103         runSimulation(m, process, "test_timeline.vcd")
 104
 105 class RoundRobinOutputMatchSpec(Elaboratable):
 106     def __init__(self, dut):
 107         self.dut = dut
 108
 109     def elaborate(self, platform):
 110         m = Module()
 111
 112         m.d.comb += Assume(Rose(self.dut.stb).implies(self.dut.request == Past(self.dut.request)))
 113
 114         m.d.sync += Assert(((Past(self.dut.request) != 0) & Past(self.dut.stb)).implies(Past(self.dut.request) & (1 << self.dut.grant)))
 115
 116         return m
 117
 118 class RoundRobinTestCase(FHDLTestCase):
 119     def test_sequence(self):
 120         m = Module()
 121         m.submodules.rb = roundrobin = RoundRobin(8)
 122
 123         def process():
 124             yield roundrobin.request.eq(0b10001000)
 125             yield roundrobin.stb.eq(1)
 126             yield
 127             yield
 128
 129             self.assertEqual((yield roundrobin.grant), 3)
 130             yield
 131
 132             self.assertEqual((yield roundrobin.grant), 7)
 133             yield
 134
 135             self.assertEqual((yield roundrobin.grant), 3)
 136             yield roundrobin.request.eq(0b00000001)
 137             yield
 138             yield
 139
 140             self.assertEqual((yield roundrobin.grant), 0)
 141
 142         runSimulation(m, process, "test_roundrobin.vcd")
 143
 144     # def test_output_match(self):
 145     #     roundrobin = RoundRobin(32)
 146     #     spec = RoundRobinOutputMatchSpec(roundrobin)
 147     #     self.assertFormal(spec, mode="bmc", depth=10)