gram/test/test_compat.py

   1 import unittest
   2 from gram.test.utils.formal import FHDLTestCase
   3
   4 from nmigen import *
   5 from nmigen.hdl.ast import Past
   6 from nmigen.asserts import Assert, Assume
   7
   8 from gram.compat import *
   9
  10 class DelayedEnterTestCase(unittest.TestCase):
  11     def test_sequence(self):
  12         def sequence(expected_delay):
  13             m = Module()
  14
  15             before = Signal()
  16             end = Signal()
  17
  18             with m.FSM():
  19                 with m.State("Before-Delayed-Enter"):
  20                     m.d.comb += before.eq(1)
  21                     m.next = "Delayed-Enter"
  22
  23                 delayed_enter(m, "Delayed-Enter", "End-Delayed-Enter", expected_delay)
  24
  25                 with m.State("End-Delayed-Enter"):
  26                     m.d.comb += end.eq(1)
  27
  28             def process():
  29                 while (yield before):
  30                     yield
  31
  32                 delay = 0
  33                 while not (yield end):
  34                     yield
  35                     delay += 1
  36
  37                 self.assertEqual(delay, expected_delay)
  38
  39             sim = Simulator(m)
  40             with sim.write_vcd("test_compat.vcd"):
  41                 sim.add_clock(1e-6)
  42                 sim.add_sync_process(process)
  43                 sim.run()
  44
  45         with self.assertRaises(AssertionError):
  46             sequence(0)
  47         sequence(1)
  48         sequence(2)
  49         sequence(10)
  50         sequence(100)
  51         sequence(1000)
  52
  53 class TimelineTestCase(unittest.TestCase):
  54     def test_sequence(self):
  55         sigA = Signal()
  56         sigB = Signal()
  57         sigC = Signal()
  58         timeline = Timeline([
  59             (1, sigA.eq(1)),
  60             (5, sigA.eq(1)),
  61             (7, sigA.eq(0)),
  62             (10, sigB.eq(1)),
  63             (11, sigB.eq(0)),
  64         ])
  65         m = Module()
  66         m.submodules.timeline = timeline
  67
  68         def process():
  69             # Test default value for unset signals
  70             self.assertFalse((yield sigA))
  71             self.assertFalse((yield sigB))
  72
  73             # Ensure that the sequence isn't triggered without the trigger signal
  74             for i in range(100):
  75                 yield
  76                 self.assertFalse((yield sigA))
  77                 self.assertFalse((yield sigB))
  78
  79             yield timeline.trigger.eq(1)
  80             yield
  81             yield timeline.trigger.eq(0)
  82
  83             for i in range(11+1):
  84                 yield
  85
  86                 if i == 1:
  87                     self.assertTrue((yield sigA))
  88                     self.assertFalse((yield sigB))
  89                 elif i == 5:
  90                     self.assertTrue((yield sigA))
  91                     self.assertFalse((yield sigB))
  92                 elif i == 7:
  93                     self.assertFalse((yield sigA))
  94                     self.assertFalse((yield sigB))
  95                 elif i == 10:
  96                     self.assertFalse((yield sigA))
  97                     self.assertTrue((yield sigB))
  98                 elif i == 11:
  99                     self.assertFalse((yield sigA))
 100                     self.assertFalse((yield sigB))
 101
 102             # Ensure no changes happen once the sequence is done
 103             for i in range(100):
 104                 yield
 105                 self.assertFalse((yield sigA))
 106                 self.assertFalse((yield sigB))
 107
 108         sim = Simulator(m)
 109         with sim.write_vcd("test_compat.vcd"):
 110             sim.add_clock(1e-6)
 111             sim.add_sync_process(process)
 112             sim.run()
 113
 114 class RoundRobinOutputMatchSpec(Elaboratable):
 115     def __init__(self, dut):
 116         self.dut = dut
 117
 118     def elaborate(self, platform):
 119         m = Module()
 120
 121         m.d.comb += Assume(Rose(self.dut.stb).implies(self.dut.request == Past(self.dut.request)))
 122
 123         m.d.sync += Assert(((Past(self.dut.request) != 0) & Past(self.dut.stb)).implies(Past(self.dut.request) & (1 << self.dut.grant)))
 124
 125         return m
 126
 127 class RoundRobinTestCase(FHDLTestCase):
 128     def test_sequence(self):
 129         m = Module()
 130         m.submodules.rb = roundrobin = RoundRobin(8)
 131
 132         def process():
 133             yield roundrobin.request.eq(0b10001000)
 134             yield roundrobin.stb.eq(1)
 135             yield
 136             yield
 137
 138             self.assertEqual((yield roundrobin.grant), 3)
 139             yield
 140
 141             self.assertEqual((yield roundrobin.grant), 7)
 142             yield
 143
 144             self.assertEqual((yield roundrobin.grant), 3)
 145             yield roundrobin.request.eq(0b00000001)
 146             yield
 147             yield
 148
 149             self.assertEqual((yield roundrobin.grant), 0)
 150
 151         sim = Simulator(m)
 152         with sim.write_vcd("test_compat.vcd"):
 153             sim.add_clock(1e-6)
 154             sim.add_sync_process(process)
 155             sim.run()
 156
 157     # def test_output_match(self):
 158     #     roundrobin = RoundRobin(32)
 159     #     spec = RoundRobinOutputMatchSpec(roundrobin)
 160     #     self.assertFormal(spec, mode="bmc", depth=10)