1 #nmigen: UnusedElaboratable=no
3 from nmigen
.hdl
.ast
import Past
4 from nmigen
.asserts
import Assert
, Assume
6 from gram
.compat
import *
9 class DelayedEnterTestCase(FHDLTestCase
):
10 def test_sequence(self
):
11 def sequence(expected_delay
):
18 with m
.State("Before-Delayed-Enter"):
19 m
.d
.comb
+= before
.eq(1)
20 m
.next
= "Delayed-Enter"
22 delayed_enter(m
, "Delayed-Enter", "End-Delayed-Enter", expected_delay
)
24 with m
.State("End-Delayed-Enter"):
32 while not (yield end
):
36 self
.assertEqual(delay
, expected_delay
)
38 runSimulation(m
, process
, "test_delayedenter.vcd")
40 with self
.assertRaises(AssertionError):
48 class TimelineTestCase(FHDLTestCase
):
49 def test_sequence(self
):
62 # Test default value for unset signals
63 self
.assertFalse((yield sigA
))
64 self
.assertFalse((yield sigB
))
66 # Ensure that the sequence isn't triggered without the trigger signal
69 self
.assertFalse((yield sigA
))
70 self
.assertFalse((yield sigB
))
72 yield timeline
.trigger
.eq(1)
74 yield timeline
.trigger
.eq(0)
80 self
.assertTrue((yield sigA
))
81 self
.assertFalse((yield sigB
))
83 self
.assertTrue((yield sigA
))
84 self
.assertFalse((yield sigB
))
86 self
.assertFalse((yield sigA
))
87 self
.assertFalse((yield sigB
))
89 self
.assertFalse((yield sigA
))
90 self
.assertTrue((yield sigB
))
92 self
.assertFalse((yield sigA
))
93 self
.assertFalse((yield sigB
))
95 # Ensure no changes happen once the sequence is done
98 self
.assertFalse((yield sigA
))
99 self
.assertFalse((yield sigB
))
101 runSimulation(timeline
, process
, "test_timeline.vcd")
103 class RoundRobinOutputMatchSpec(Elaboratable
):
104 def __init__(self
, dut
):
107 def elaborate(self
, platform
):
110 m
.d
.comb
+= Assume(Rose(self
.dut
.stb
).implies(self
.dut
.request
== Past(self
.dut
.request
)))
112 m
.d
.sync
+= Assert(((Past(self
.dut
.request
) != 0) & Past(self
.dut
.stb
)).implies(Past(self
.dut
.request
) & (1 << self
.dut
.grant
)))
116 class RoundRobinTestCase(FHDLTestCase
):
117 def test_sequence(self
):
119 m
.submodules
.rb
= roundrobin
= RoundRobin(8)
122 yield roundrobin
.request
.eq(0b10001000)
123 yield roundrobin
.stb
.eq(1)
127 self
.assertEqual((yield roundrobin
.grant
), 3)
130 self
.assertEqual((yield roundrobin
.grant
), 7)
133 self
.assertEqual((yield roundrobin
.grant
), 3)
134 yield roundrobin
.request
.eq(0b00000001)
138 self
.assertEqual((yield roundrobin
.grant
), 0)
140 runSimulation(m
, process
, "test_roundrobin.vcd")
142 # def test_output_match(self):
143 # roundrobin = RoundRobin(32)
144 # spec = RoundRobinOutputMatchSpec(roundrobin)
145 # self.assertFormal(spec, mode="bmc", depth=10)