Fix memtest tests (missing parenthesis)
[gram.git] / gram / test / test_core_refresher.py
1 from nmigen import *
2 from nmigen.hdl.ast import Past
3 from nmigen.asserts import Assert, Assume
4
5 from gram.core.refresher import RefreshExecuter, RefreshSequencer, RefreshTimer, RefreshPostponer, Refresher
6 from gram.compat import *
7 from utils import *
8
9 class RefreshExecuterTestCase(FHDLTestCase):
10 def test_executer(self):
11 def generic_test(abits, babits, trp, trfc):
12 m = Module()
13 m.submodules.dut = dut = RefreshExecuter(abits=abits, babits=babits, trp=trp, trfc=trfc)
14
15 def process():
16 yield dut.start.eq(1)
17 yield
18 yield
19 self.assertEqual((yield dut.a), 2**10)
20 for i in range(trp):
21 yield
22 self.assertEqual((yield dut.a), 0)
23
24 runSimulation(m, process, "test_refreshexecuter.vcd")
25
26 generic_test(20, 20, 5, 5)
27 generic_test(20, 20, 100, 5)
28
29 class RefreshSequencerTestCase(FHDLTestCase):
30 def test_formal(self):
31 dut = RefreshSequencer(abits=14, babits=3, trp=5, trfc=5, postponing=1)
32 self.assertFormal(dut, mode="bmc", depth=4)
33
34 class RefreshTimerTestCase(FHDLTestCase):
35 def test_formal(self):
36 def generic_test(tREFI):
37 dut = RefreshTimer(tREFI)
38 self.assertFormal(dut, mode="bmc", depth=4)
39 [generic_test(_) for _ in [2, 5, 10]]
40
41 class RefreshPostponerTestCase(FHDLTestCase):
42 def test_init(self):
43 m = Module()
44 m.submodules.dut = dut = RefreshPostponer(1)
45
46 def process():
47 self.assertFalse((yield dut.req_o))
48
49 runSimulation(m, process, "test_refreshpostponer.vcd")
50
51 def test_delay(self):
52 def generic_test(delay):
53 m = Module()
54 m.submodules.dut = dut = RefreshPostponer(delay)
55
56 def process():
57 yield dut.req_i.eq(1)
58 yield
59
60 for i in range(delay):
61 self.assertFalse((yield dut.req_o))
62 yield
63
64 self.assertTrue((yield dut.req_o))
65
66 runSimulation(m, process, "test_refreshpostponer.vcd")
67
68 [generic_test(_) for _ in [1, 5, 10]]
69
70 def test_req_not_stuck(self):
71 def generic_test(delay):
72 m = Module()
73 m.submodules.dut = dut = RefreshPostponer(delay)
74
75 def process():
76 yield dut.req_i.eq(1)
77 yield
78
79 for i in range(delay):
80 yield
81
82 yield dut.req_i.eq(0)
83 yield
84 yield
85
86 self.assertFalse((yield dut.req_o))
87
88 runSimulation(m, process, "test_refreshpostponer.vcd")
89
90 [generic_test(_) for _ in [1, 5, 10]]
91
92 class RefresherTestCase(FHDLTestCase):
93 class Obj:
94 pass
95
96 settings = Obj()
97 settings.with_refresh = True
98 settings.refresh_zqcs_freq = 1e0
99 settings.timing = Obj()
100 settings.timing.tREFI = 64
101 settings.timing.tRP = 1
102 settings.timing.tRFC = 2
103 settings.timing.tZQCS = 64
104 settings.geom = Obj()
105 settings.geom.addressbits = 16
106 settings.geom.bankbits = 3
107 settings.phy = Obj()
108 settings.phy.nranks = 1
109
110 def test_init(self):
111 def generic_test(postponing):
112 m = Module()
113 m.submodules.dut = dut = Refresher(self.settings, 100e6, postponing)
114
115 def process():
116 self.assertFalse((yield dut.cmd.valid))
117
118 runSimulation(m, process, "test_refresher.vcd")
119
120 [generic_test(_) for _ in [1, 2, 4, 8]]