gram/test/test_dfii.py

   1 from nmigen import *
   2 from nmigen.hdl.ast import Past
   3 from nmigen.asserts import Assert, Assume
   4 from lambdasoc.periph import Peripheral
   5
   6 from gram.dfii import *
   7 from gram.phy.dfi import Interface
   8 from utils import *
   9
  10 class CSRHost(Peripheral, Elaboratable):
  11     def __init__(self, name="csrhost"):
  12         super().__init__(name=name)
  13         self.bank = self.csr_bank()
  14
  15     def init_bridge(self):
  16         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
  17         self.bus = self._bridge.bus
  18
  19     def elaborate(self, platform):
  20         m = Module()
  21         m.submodules += self._bridge
  22         return m
  23
  24 class PhaseInjectorTestCase(FHDLTestCase):
  25     def generate_phaseinjector(self):
  26         dfi = Interface(12, 8, 1, 8, 1)
  27         csrhost = CSRHost()
  28         dut = PhaseInjector(csrhost.bank, dfi.phases[0])
  29         csrhost.init_bridge()
  30         m = Module()
  31         m.submodules += csrhost
  32         m.submodules += dut
  33
  34         return (m, dfi, csrhost)
  35
  36     def test_initialstate(self):
  37         m, dfi, csrhost = self.generate_phaseinjector()
  38
  39         def process():
  40             self.assertTrue((yield dfi.phases[0].cas_n))
  41             self.assertTrue((yield dfi.phases[0].ras_n))
  42             self.assertTrue((yield dfi.phases[0].we_n))
  43             self.assertTrue((yield dfi.phases[0].act_n))
  44
  45         runSimulation(m, process, "test_phaseinjector.vcd")
  46
  47     def test_setaddress(self):
  48         m, dfi, csrhost = self.generate_phaseinjector()
  49
  50         def process():
  51             yield from wb_write(csrhost.bus, 0x8 >> 2, 0xCDC, sel=0xF)
  52             self.assertEqual((yield dfi.phases[0].address), 0xCDC)
  53
  54         runSimulation(m, process, "test_phaseinjector.vcd")