gram/test/test_dfii.py

   1 from nmigen import *
   2 from lambdasoc.periph import Peripheral
   3
   4 from gram.dfii import *
   5 from gram.phy.dfi import Interface
   6 from utils import *
   7
   8 # Phase injector CSR addresses
   9 PI_COMMAND_ADDR = 0x00
  10 PI_COMMAND_ISSUE_ADDR = 0x04
  11 PI_ADDRESS_ADDR = 0x08
  12 PI_BADDRESS_ADDR = 0x0C
  13 PI_WRDATA_ADDR = 0x10
  14 PI_RDDATA_ADDR = 0x14
  15
  16 # DFI injector CSR addresses
  17 DFII_CONTROL_ADDR = 0x00
  18
  19 class CSRHost(Peripheral, Elaboratable):
  20     def __init__(self, name="csrhost"):
  21         super().__init__(name=name)
  22         self.bank = self.csr_bank()
  23
  24     def init_bridge(self):
  25         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
  26         self.bus = self._bridge.bus
  27
  28     def elaborate(self, platform):
  29         m = Module()
  30         m.submodules += self._bridge
  31         return m
  32
  33 class PhaseInjectorTestCase(FHDLTestCase):
  34     def generate_phaseinjector(self):
  35         dfi = Interface(12, 8, 1, 8, 1)
  36         csrhost = CSRHost()
  37         dut = PhaseInjector(csrhost.bank, dfi.phases[0])
  38         csrhost.init_bridge()
  39         m = Module()
  40         m.submodules += csrhost
  41         m.submodules += dut
  42
  43         return (m, dfi, csrhost)
  44
  45     def test_initialstate(self):
  46         m, dfi, csrhost = self.generate_phaseinjector()
  47
  48         def process():
  49             self.assertTrue((yield dfi.phases[0].cas_n))
  50             self.assertTrue((yield dfi.phases[0].ras_n))
  51             self.assertTrue((yield dfi.phases[0].we_n))
  52             self.assertTrue((yield dfi.phases[0].act_n))
  53             self.assertFalse((yield dfi.phases[0].wrdata_mask))
  54
  55         runSimulation(m, process, "test_phaseinjector.vcd")
  56
  57     def test_setaddress(self):
  58         m, dfi, csrhost = self.generate_phaseinjector()
  59
  60         def process():
  61             yield from wb_write(csrhost.bus, PI_ADDRESS_ADDR >> 2, 0xCDC, sel=0xF)
  62             self.assertEqual((yield dfi.phases[0].address), 0xCDC)
  63
  64         runSimulation(m, process, "test_phaseinjector.vcd")
  65
  66     def test_setbankaddress(self):
  67         m, dfi, csrhost = self.generate_phaseinjector()
  68
  69         def process():
  70             yield from wb_write(csrhost.bus, PI_BADDRESS_ADDR >> 2, 0xA8, sel=0xF)
  71             self.assertEqual((yield dfi.phases[0].bank), 0xA8)
  72
  73         runSimulation(m, process, "test_phaseinjector.vcd")
  74
  75     def test_setwrdata(self):
  76         m, dfi, csrhost = self.generate_phaseinjector()
  77
  78         def process():
  79             yield from wb_write(csrhost.bus, PI_WRDATA_ADDR >> 2, 0xCC, sel=0xF)
  80             self.assertEqual((yield dfi.phases[0].wrdata), 0xCC)
  81
  82         runSimulation(m, process, "test_phaseinjector.vcd")
  83
  84     def test_wrdata_en(self):
  85         m, dfi, csrhost = self.generate_phaseinjector()
  86
  87         m.submodules.pc = pc = PulseCounter()
  88         m.d.comb += pc.i.eq(dfi.phases[0].wrdata_en)
  89
  90         def process():
  91             yield from wb_write(csrhost.bus, PI_COMMAND_ADDR >> 2, (1 << 4), sel=0xF)
  92             yield
  93             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
  94             self.assertEqual((yield pc.cnt), 1)
  95             yield
  96             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
  97             self.assertEqual((yield pc.cnt), 2)
  98
  99         runSimulation(m, process, "test_phaseinjector.vcd")
 100
 101     def test_rddata_en(self):
 102         m, dfi, csrhost = self.generate_phaseinjector()
 103
 104         m.submodules.pc = pc = PulseCounter()
 105         m.d.comb += pc.i.eq(dfi.phases[0].rddata_en)
 106
 107         def process():
 108             yield from wb_write(csrhost.bus, PI_COMMAND_ADDR >> 2, (1 << 5), sel=0xF)
 109             yield
 110             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
 111             self.assertEqual((yield pc.cnt), 1)
 112             yield
 113             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
 114             self.assertEqual((yield pc.cnt), 2)
 115
 116         runSimulation(m, process, "test_phaseinjector.vcd")