2 from lambdasoc
.periph
import Peripheral
4 from gram
.dfii
import *
5 from gram
.phy
.dfi
import Interface
8 # Phase injector CSR addresses
10 PI_COMMAND_ISSUE_ADDR
= 0x04
11 PI_ADDRESS_ADDR
= 0x08
12 PI_BADDRESS_ADDR
= 0x0C
16 # DFI injector CSR addresses
17 DFII_CONTROL_ADDR
= 0x00
19 class CSRHost(Peripheral
, Elaboratable
):
20 def __init__(self
, name
="csrhost"):
21 super().__init
__(name
=name
)
22 self
.bank
= self
.csr_bank()
24 def init_bridge(self
):
25 self
._bridge
= self
.bridge(data_width
=32, granularity
=8, alignment
=2)
26 self
.bus
= self
._bridge
.bus
28 def elaborate(self
, platform
):
30 m
.submodules
+= self
._bridge
33 class PhaseInjectorTestCase(FHDLTestCase
):
34 def generate_phaseinjector(self
):
35 dfi
= Interface(12, 8, 1, 8, 1)
37 dut
= PhaseInjector(csrhost
.bank
, dfi
.phases
[0])
40 m
.submodules
+= csrhost
43 return (m
, dfi
, csrhost
)
45 def test_initialstate(self
):
46 m
, dfi
, csrhost
= self
.generate_phaseinjector()
49 self
.assertTrue((yield dfi
.phases
[0].cas_n
))
50 self
.assertTrue((yield dfi
.phases
[0].ras_n
))
51 self
.assertTrue((yield dfi
.phases
[0].we_n
))
52 self
.assertTrue((yield dfi
.phases
[0].act_n
))
53 self
.assertFalse((yield dfi
.phases
[0].wrdata_mask
))
54 self
.assertFalse((yield dfi
.phases
[0].rddata_en
))
55 self
.assertFalse((yield dfi
.phases
[0].wrdata_en
))
57 runSimulation(m
, process
, "test_phaseinjector.vcd")
59 def test_setaddress(self
):
60 m
, dfi
, csrhost
= self
.generate_phaseinjector()
63 yield from wb_write(csrhost
.bus
, PI_ADDRESS_ADDR
>> 2, 0xCDC, sel
=0xF)
64 self
.assertEqual((yield dfi
.phases
[0].address
), 0xCDC)
66 runSimulation(m
, process
, "test_phaseinjector.vcd")
68 def test_setbankaddress(self
):
69 m
, dfi
, csrhost
= self
.generate_phaseinjector()
72 yield from wb_write(csrhost
.bus
, PI_BADDRESS_ADDR
>> 2, 0xA8, sel
=0xF)
73 self
.assertEqual((yield dfi
.phases
[0].bank
), 0xA8)
75 runSimulation(m
, process
, "test_phaseinjector.vcd")
77 def test_setwrdata(self
):
78 m
, dfi
, csrhost
= self
.generate_phaseinjector()
81 yield from wb_write(csrhost
.bus
, PI_WRDATA_ADDR
>> 2, 0xCC, sel
=0xF)
82 self
.assertEqual((yield dfi
.phases
[0].wrdata
), 0xCC)
84 runSimulation(m
, process
, "test_phaseinjector.vcd")
86 def test_wrdata_en(self
):
87 m
, dfi
, csrhost
= self
.generate_phaseinjector()
89 m
.submodules
.pc
= pc
= PulseCounter()
90 m
.d
.comb
+= pc
.i
.eq(dfi
.phases
[0].wrdata_en
)
93 yield from wb_write(csrhost
.bus
, PI_COMMAND_ADDR
>> 2, (1 << 4), sel
=0xF)
95 yield from wb_write(csrhost
.bus
, PI_COMMAND_ISSUE_ADDR
>> 2, 1, sel
=0xF)
96 self
.assertEqual((yield pc
.cnt
), 1)
98 yield from wb_write(csrhost
.bus
, PI_COMMAND_ISSUE_ADDR
>> 2, 1, sel
=0xF)
99 self
.assertEqual((yield pc
.cnt
), 2)
101 runSimulation(m
, process
, "test_phaseinjector.vcd")
103 def test_rddata_en(self
):
104 m
, dfi
, csrhost
= self
.generate_phaseinjector()
106 m
.submodules
.pc
= pc
= PulseCounter()
107 m
.d
.comb
+= pc
.i
.eq(dfi
.phases
[0].rddata_en
)
110 yield from wb_write(csrhost
.bus
, PI_COMMAND_ADDR
>> 2, (1 << 5), sel
=0xF)
112 yield from wb_write(csrhost
.bus
, PI_COMMAND_ISSUE_ADDR
>> 2, 1, sel
=0xF)
113 self
.assertEqual((yield pc
.cnt
), 1)
115 yield from wb_write(csrhost
.bus
, PI_COMMAND_ISSUE_ADDR
>> 2, 1, sel
=0xF)
116 self
.assertEqual((yield pc
.cnt
), 2)
118 runSimulation(m
, process
, "test_phaseinjector.vcd")
120 class DFIInjectorTestCase(FHDLTestCase
):
121 def generate_dfiinjector(self
):
123 dut
= DFIInjector(csrhost
.bank
, 14, 3, 1, 16, nphases
=1)
124 csrhost
.init_bridge()
126 m
.submodules
+= csrhost
129 return (m
, dut
, csrhost
)
132 m
, dut
, csrhost
= self
.generate_dfiinjector()
135 yield from wb_write(csrhost
.bus
, DFII_CONTROL_ADDR
>> 2, (1 << 1), sel
=0xF)
137 self
.assertTrue((yield dut
.master
.phases
[0].cke
[0]))
139 yield from wb_write(csrhost
.bus
, DFII_CONTROL_ADDR
>> 2, 0, sel
=0xF)
141 self
.assertFalse((yield dut
.master
.phases
[0].cke
[0]))
143 runSimulation(m
, process
, "test_dfiinjector.vcd")