gram/test/test_dfii.py

   1 from nmigen import *
   2 from lambdasoc.periph import Peripheral
   3
   4 from gram.dfii import *
   5 from gram.phy.dfi import Interface
   6 from utils import *
   7
   8 # Phase injector CSR addresses
   9 PI_COMMAND_ADDR = 0x00
  10 PI_COMMAND_ISSUE_ADDR = 0x04
  11 PI_ADDRESS_ADDR = 0x08
  12 PI_BADDRESS_ADDR = 0x0C
  13 PI_WRDATA_ADDR = 0x10
  14 PI_RDDATA_ADDR = 0x14
  15
  16 # DFI injector CSR addresses
  17 DFII_CONTROL_ADDR = 0x00
  18
  19 class CSRHost(Peripheral, Elaboratable):
  20     def __init__(self, name="csrhost"):
  21         super().__init__(name=name)
  22         self.bank = self.csr_bank()
  23
  24     def init_bridge(self):
  25         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
  26         self.bus = self._bridge.bus
  27
  28     def elaborate(self, platform):
  29         m = Module()
  30         m.submodules += self._bridge
  31         return m
  32
  33 class PhaseInjectorTestCase(FHDLTestCase):
  34     def generate_phaseinjector(self):
  35         dfi = Interface(12, 8, 1, 8, 1)
  36         csrhost = CSRHost()
  37         dut = PhaseInjector(csrhost.bank, dfi.phases[0])
  38         csrhost.init_bridge()
  39         m = Module()
  40         m.submodules += csrhost
  41         m.submodules += dut
  42
  43         return (m, dfi, csrhost)
  44
  45     def test_initialstate(self):
  46         m, dfi, csrhost = self.generate_phaseinjector()
  47
  48         def process():
  49             self.assertTrue((yield dfi.phases[0].cas_n))
  50             self.assertTrue((yield dfi.phases[0].ras_n))
  51             self.assertTrue((yield dfi.phases[0].we_n))
  52             self.assertTrue((yield dfi.phases[0].act_n))
  53
  54         runSimulation(m, process, "test_phaseinjector.vcd")
  55
  56     def test_setaddress(self):
  57         m, dfi, csrhost = self.generate_phaseinjector()
  58
  59         def process():
  60             yield from wb_write(csrhost.bus, PI_ADDRESS_ADDR >> 2, 0xCDC, sel=0xF)
  61             self.assertEqual((yield dfi.phases[0].address), 0xCDC)
  62
  63         runSimulation(m, process, "test_phaseinjector.vcd")
  64
  65     def test_setbankaddress(self):
  66         m, dfi, csrhost = self.generate_phaseinjector()
  67
  68         def process():
  69             yield from wb_write(csrhost.bus, PI_BADDRESS_ADDR >> 2, 0xA8, sel=0xF)
  70             self.assertEqual((yield dfi.phases[0].bank), 0xA8)
  71
  72         runSimulation(m, process, "test_phaseinjector.vcd")
  73
  74     def test_setwrdata(self):
  75         m, dfi, csrhost = self.generate_phaseinjector()
  76
  77         def process():
  78             yield from wb_write(csrhost.bus, PI_WRDATA_ADDR >> 2, 0xCC, sel=0xF)
  79             self.assertEqual((yield dfi.phases[0].wrdata), 0xCC)
  80
  81         runSimulation(m, process, "test_phaseinjector.vcd")
  82
  83     def test_wrdata_en(self):
  84         m, dfi, csrhost = self.generate_phaseinjector()
  85
  86         m.submodules.pc = pc = PulseCounter()
  87         m.d.comb += pc.i.eq(dfi.phases[0].wrdata_en)
  88
  89         def process():
  90             yield from wb_write(csrhost.bus, PI_COMMAND_ADDR >> 2, (1 << 4), sel=0xF)
  91             yield
  92             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
  93             self.assertEqual((yield pc.cnt), 1)
  94             yield
  95             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
  96             self.assertEqual((yield pc.cnt), 2)
  97
  98
  99         runSimulation(m, process, "test_phaseinjector.vcd")