1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
6 from nmigen
.asserts
import Assert
, Assume
7 from nmigen_soc
import wishbone
, memory
8 from nmigen
.lib
.cdc
import ResetSynchronizer
10 from lambdasoc
.periph
import Peripheral
11 from lambdasoc
.soc
.base
import SoC
13 from gram
.common
import *
14 from gram
.core
import gramCore
15 from gram
.phy
.fakephy
import FakePHY
, SDRAM_VERBOSE_STD
, SDRAM_VERBOSE_DBG
16 from gram
.modules
import MT41K256M16
17 from gram
.frontend
.wishbone
import gramWishbone
19 from gram
.core
.multiplexer
import _AntiStarvation
22 class DDR3SoC(SoC
, Elaboratable
):
23 def __init__(self
, *, clk_freq
, dramcore_addr
,
25 self
._arbiter
= wishbone
.Arbiter(addr_width
=30, data_width
=32, granularity
=8,
26 features
={"cti", "bte"})
27 self
._decoder
= wishbone
.Decoder(addr_width
=30, data_width
=32, granularity
=8,
28 features
={"cti", "bte"})
30 self
.bus
= wishbone
.Interface(addr_width
=30, data_width
=32, granularity
=32)
31 self
._arbiter
.add(self
.bus
)
39 cl
, cwl
= get_cl_cw("DDR3", tck
)
40 cl_sys_latency
= get_sys_latency(nphases
, cl
)
41 cwl_sys_latency
= get_sys_latency(nphases
, cwl
)
42 rdcmdphase
, rdphase
= get_sys_phases(nphases
, cl_sys_latency
, cl
)
43 wrcmdphase
, wrphase
= get_sys_phases(nphases
, cwl_sys_latency
, cwl
)
44 physettings
= PhySettings(
48 dfi_databits
=4*databits
,
53 rdcmdphase
=rdcmdphase
,
54 wrcmdphase
=wrcmdphase
,
57 read_latency
=2 + cl_sys_latency
+ 2 + log2_int(4//nphases
) + 4,
58 write_latency
=cwl_sys_latency
61 ddrmodule
= MT41K256M16(clk_freq
, "1:4")
62 self
.ddrphy
= FakePHY(module
=ddrmodule
,
64 verbosity
=SDRAM_VERBOSE_DBG
)
66 self
.dramcore
= gramCore(
68 geom_settings
=ddrmodule
.geom_settings
,
69 timing_settings
=ddrmodule
.timing_settings
,
71 self
._decoder
.add(self
.dramcore
.bus
, addr
=dramcore_addr
)
73 self
.drambone
= gramWishbone(self
.dramcore
)
74 self
._decoder
.add(self
.drambone
.bus
, addr
=ddr_addr
)
76 self
.memory_map
= self
._decoder
.bus
.memory_map
78 self
.clk_freq
= clk_freq
80 def elaborate(self
, platform
):
83 m
.submodules
.arbiter
= self
._arbiter
85 m
.submodules
.decoder
= self
._decoder
86 m
.submodules
.ddrphy
= self
.ddrphy
87 m
.submodules
.dramcore
= self
.dramcore
88 m
.submodules
.drambone
= self
.drambone
91 self
._arbiter
.bus
.connect(self
._decoder
.bus
),
96 class SocTestCase(FHDLTestCase
):
98 yield from wb_write(bus
, 0x0, 0xE, 0xF) # DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
99 yield from wb_write(bus
, 0xC >> 2, 0x0, 0xF)
100 yield from wb_write(bus
, 0x10 >> 2, 0x0, 0xF)
101 yield from wb_write(bus
, 0x0, 0xC, 0xF)
102 yield from wb_write(bus
, 0x0, 0xE, 0xF)
105 yield from wb_write(bus
, 0xC >> 2, 0x200, 0xF)
106 yield from wb_write(bus
, 0x10 >> 2, 0x2, 0xF)
107 yield from wb_write(bus
, 0x4 >> 2, 0xF, 0xF)
108 yield from wb_write(bus
, 0x8 >> 2, 0x1, 0xF)
111 yield from wb_write(bus
, 0xC >> 2, 0x0, 0xF)
112 yield from wb_write(bus
, 0x10 >> 2, 0x3, 0xF)
113 yield from wb_write(bus
, 0x4 >> 2, 0xF, 0xF)
114 yield from wb_write(bus
, 0x8 >> 2, 0x1, 0xF)
117 yield from wb_write(bus
, 0xC >> 2, 0x6, 0xF)
118 yield from wb_write(bus
, 0x10 >> 2, 0x1, 0xF)
119 yield from wb_write(bus
, 0x4 >> 2, 0xF, 0xF)
120 yield from wb_write(bus
, 0x8 >> 2, 0x1, 0xF)
123 yield from wb_write(bus
, 0xC >> 2, 0x320, 0xF)
124 yield from wb_write(bus
, 0x10 >> 2, 0x0, 0xF)
125 yield from wb_write(bus
, 0x4 >> 2, 0xF, 0xF)
126 yield from wb_write(bus
, 0x8 >> 2, 0x1, 0xF)
131 yield from wb_write(bus
, 0xC >> 2, 0x400, 0xF)
132 yield from wb_write(bus
, 0x10 >> 2, 0x0, 0xF)
133 yield from wb_write(bus
, 0x4 >> 2, 0x3, 0xF)
134 yield from wb_write(bus
, 0x8 >> 2, 0x1, 0xF)
138 yield from wb_write(bus
, 0, 0x1, 0xF)
139 for i
in range(2000):
142 def test_multiple_reads(self
):
144 soc
= DDR3SoC(clk_freq
=100e6
,
145 dramcore_addr
=0x00000000,
150 yield from SocTestCase
.init_seq(soc
.bus
)
152 yield from wb_write(soc
.bus
, 0x10000000 >> 2, 0xACAB2020, 0xF, 128)
155 # Check for data persistence
157 res
= yield from wb_read(soc
.bus
, 0x10000000 >> 2, 0xF, 128)
159 self
.assertEqual(res
, 0xACAB2020)
161 runSimulation(m
, process
, "test_soc_multiple_reads.vcd")
163 def test_interleaved_read_write(self
):
165 soc
= DDR3SoC(clk_freq
=100e6
,
166 dramcore_addr
=0x00000000,
171 yield from SocTestCase
.init_seq(soc
.bus
)
173 yield from wb_write(soc
.bus
, 0x10000000 >> 2, 0xF00DFACE, 0xF, 128)
174 yield from wb_write(soc
.bus
, 0x10000004 >> 2, 0x12345678, 0xF, 128)
175 yield from wb_write(soc
.bus
, 0x10000008 >> 2, 0x00BA0BAB, 0xF, 128)
177 res
= yield from wb_read(soc
.bus
, 0x10000000 >> 2, 0xF, 128)
178 self
.assertEqual(res
, 0xF00DFACE)
180 yield from wb_write(soc
.bus
, 0x10000008 >> 2, 0xCAFE1000, 0xF, 128)
182 res
= yield from wb_read(soc
.bus
, 0x10000004 >> 2, 0xF, 128)
183 self
.assertEqual(res
, 0x12345678)
185 res
= yield from wb_read(soc
.bus
, 0x10000008 >> 2, 0xF, 128)
186 self
.assertEqual(res
, 0xCAFE1000)
188 runSimulation(m
, process
, "test_soc_interleaved_read_write.vcd")
190 def test_sequential_reads(self
):
192 soc
= DDR3SoC(clk_freq
=100e6
,
193 dramcore_addr
=0x00000000,
198 yield from SocTestCase
.init_seq(soc
.bus
)
200 # Should read from same row/col/bank
201 yield from wb_read(soc
.bus
, 0x10000000 >> 2, 0xF, 128)
202 yield from wb_read(soc
.bus
, 0x10000004 >> 2, 0xF, 128)
203 yield from wb_read(soc
.bus
, 0x10000008 >> 2, 0xF, 128)
204 yield from wb_read(soc
.bus
, 0x1000000C >> 2, 0xF, 128)
206 # Should read from a different row
207 yield from wb_read(soc
.bus
, 0x10000010 >> 2, 0xF, 128)
208 yield from wb_read(soc
.bus
, 0x10000014 >> 2, 0xF, 128)
209 yield from wb_read(soc
.bus
, 0x10000018 >> 2, 0xF, 128)
210 yield from wb_read(soc
.bus
, 0x1000001C >> 2, 0xF, 128)
212 runSimulation(m
, process
, "test_soc_sequential_reads.vcd")
214 def test_random_memtest(self
):
216 soc
= DDR3SoC(clk_freq
=100e6
,
217 dramcore_addr
=0x00000000,
222 yield from SocTestCase
.init_seq(soc
.bus
)
228 memtest_values
.append(random
.randint(0, 0xFFFFFFFF))
232 yield from wb_write(soc
.bus
, 0x10000000 >> 2 + i
, memtest_values
[i
], 0xF, 256)
236 self
.assertEqual(memtest_values
[i
], (yield from wb_read(soc
.bus
, 0x10000000 >> 2 + i
, 0xF, 256)))
238 runSimulation(m
, process
, "test_soc_random_memtest.vcd")
240 def test_continuous_memtest(self
):
242 soc
= DDR3SoC(clk_freq
=100e6
,
243 dramcore_addr
=0x00000000,
248 yield from SocTestCase
.init_seq(soc
.bus
)
254 yield from wb_write(soc
.bus
, 0x10000000 >> 2 + i
, 0xFACE0000 | i
, 0xF, 256)
258 self
.assertEqual(0xFACE0000 | i
, (yield from wb_read(soc
.bus
, 0x10000000 >> 2 + i
, 0xF, 256)))
260 runSimulation(m
, process
, "test_soc_continuous_memtest.vcd")