b1cf7fc81ce159d67a85f633a335c43af8966939
[riscv-isa-sim.git] / hwacha / hwacha.cc
1 #include "hwacha.h"
2 #include "hwacha_xcpt.h"
3 #include "trap.h"
4
5 void ct_state_t::reset()
6 {
7 vl = 0;
8 maxvl = 32;
9 nxpr = 32;
10 nfpr = 32;
11
12 vf_pc = -1;
13
14 cause = 0;
15 aux = 0;
16 }
17
18 void ut_state_t::reset()
19 {
20 run = false;
21 XPR.reset();
22 FPR.reset();
23 }
24
25 void hwacha_t::reset()
26 {
27 ct_state.reset();
28 for (int i=0; i<max_uts; i++)
29 ut_state[i].reset();
30 }
31
32 static reg_t custom(processor_t* p, insn_t insn, reg_t pc)
33 {
34 hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
35 bool matched = false;
36 reg_t npc = -1;
37
38 try
39 {
40 #define DECLARE_INSN(name, match, mask) \
41 extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
42 if ((insn.bits() & mask) == match) { \
43 npc = hwacha_##name(p, insn, pc); \
44 matched = true; \
45 }
46 #include "opcodes_hwacha.h"
47 #undef DECLARE_INSN
48 }
49 catch (trap_instruction_access_fault& t)
50 {
51 h->take_exception(HWACHA_CAUSE_VF_FAULT_FETCH, h->get_ct_state()->vf_pc);
52 }
53 catch (trap_load_address_misaligned& t)
54 {
55 h->take_exception(HWACHA_CAUSE_MISALIGNED_LOAD, t.get_badvaddr());
56 }
57 catch (trap_store_address_misaligned& t)
58 {
59 h->take_exception(HWACHA_CAUSE_MISALIGNED_STORE, t.get_badvaddr());
60 }
61 catch (trap_load_access_fault& t)
62 {
63 h->take_exception(HWACHA_CAUSE_FAULT_LOAD, t.get_badvaddr());
64 }
65 catch (trap_store_access_fault& t)
66 {
67 h->take_exception(HWACHA_CAUSE_FAULT_STORE, t.get_badvaddr());
68 }
69
70 if (!matched)
71 h->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION, insn.bits());
72
73 return npc;
74 }
75
76 std::vector<insn_desc_t> hwacha_t::get_instructions()
77 {
78 std::vector<insn_desc_t> insns;
79 insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, custom});
80 insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, custom});
81 insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, custom});
82 insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, custom});
83 return insns;
84 }
85
86 bool hwacha_t::vf_active()
87 {
88 for (uint32_t i=0; i<get_ct_state()->vl; i++) {
89 if (get_ut_state(i)->run)
90 return true;
91 }
92 return false;
93 }
94
95 void hwacha_t::take_exception(reg_t cause, reg_t aux)
96 {
97 get_ct_state()->cause = cause;
98 get_ct_state()->aux = aux;
99 raise_interrupt();
100 if (!(p->get_state()->sr & SR_EI))
101 throw std::logic_error("hwacha exception posted, but SR_EI bit not set!");
102 throw std::logic_error("hwacha exception posted, but IM[COP] bit not set!");
103 }