2 -- Set associative icache
4 -- TODO (in no specific order):
6 -- * Add debug interface to inspect cache content
7 -- * Add snoop/invalidate path
8 -- * Add multi-hit error detection
9 -- * Pipelined bus interface (wb or axi)
10 -- * Maybe add parity ? There's a few bits free in each BRAM row on Xilinx
11 -- * Add optimization: service hits on partially loaded lines
12 -- * Add optimization: (maybe) interrupt reload on fluch/redirect
13 -- * Check if playing with the geometry of the cache tags allow for more
14 -- efficient use of distributed RAM and less logic/muxes. Currently we
15 -- write TAG_BITS width which may not match full ram blocks and might
16 -- cause muxes to be inferred for "partial writes".
17 -- * Check if making the read size of PLRU a ROM helps utilization
20 use ieee.std_logic_1164.all;
21 use ieee.numeric_std.all;
26 use work.wishbone_types.all;
28 -- 64 bit direct mapped icache. All instructions are 4B aligned.
32 SIM : boolean := false;
34 LINE_SIZE : positive := 64;
35 -- BRAM organisation: We never access more than wishbone_data_bits at
36 -- a time so to save resources we make the array only that wide, and
37 -- use consecutive indices for to make a cache "line"
39 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
40 ROW_SIZE : positive := wishbone_data_bits / 8;
41 -- Number of lines in a set
42 NUM_LINES : positive := 32;
44 NUM_WAYS : positive := 4;
45 -- L1 ITLB number of entries (direct mapped)
46 TLB_SIZE : positive := 64;
47 -- L1 ITLB log_2(page_size)
48 TLB_LG_PGSZ : positive := 12;
49 -- Number of real address bits that we store
50 REAL_ADDR_BITS : positive := 56;
51 -- Non-zero to enable log data collection
52 LOG_LENGTH : natural := 0
58 i_in : in Fetch1ToIcacheType;
59 i_out : out IcacheToDecode1Type;
61 m_in : in MmuToIcacheType;
63 stall_in : in std_ulogic;
64 stall_out : out std_ulogic;
65 flush_in : in std_ulogic;
66 inval_in : in std_ulogic;
68 wishbone_out : out wishbone_master_out;
69 wishbone_in : in wishbone_slave_out;
71 log_out : out std_ulogic_vector(53 downto 0)
75 architecture rtl of icache is
76 constant ROW_SIZE_BITS : natural := ROW_SIZE*8;
77 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
78 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
79 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
81 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
82 -- INSN_PER_ROW is the number of 32bit instructions per BRAM row
83 constant INSN_PER_ROW : natural := ROW_SIZE_BITS / 32;
84 -- Bit fields counts in the address
86 -- INSN_BITS is the number of bits to select an instruction in a row
87 constant INSN_BITS : natural := log2(INSN_PER_ROW);
88 -- ROW_BITS is the number of bits to select a row
89 constant ROW_BITS : natural := log2(BRAM_ROWS);
90 -- ROW_LINEBITS is the number of bits to select a row within a line
91 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
92 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
93 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
94 -- ROW_OFF_BITS is the number of bits for the offset in a row
95 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
96 -- INDEX_BITS is the number of bits to select a cache line
97 constant INDEX_BITS : natural := log2(NUM_LINES);
98 -- SET_SIZE_BITS is the log base 2 of the set size
99 constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
100 -- TAG_BITS is the number of bits of the tag part of the address
101 -- the +1 is to allow the endianness to be stored in the tag
102 constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS + 1;
103 -- WAY_BITS is the number of bits to select a way
104 constant WAY_BITS : natural := log2(NUM_WAYS);
106 -- Example of layout for 32 lines of 64 bytes:
108 -- .. tag |index| line |
110 -- .. | | | |00| zero (2)
111 -- .. | | |-| | INSN_BITS (1)
112 -- .. | |---| | ROW_LINEBITS (3)
113 -- .. | |--- - --| LINE_OFF_BITS (6)
114 -- .. | |- --| ROW_OFF_BITS (3)
115 -- .. |----- ---| | ROW_BITS (8)
116 -- .. |-----| | INDEX_BITS (5)
117 -- .. --------| | TAG_BITS (53)
119 subtype row_t is integer range 0 to BRAM_ROWS-1;
120 subtype index_t is integer range 0 to NUM_LINES-1;
121 subtype way_t is integer range 0 to NUM_WAYS-1;
122 subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
124 -- The cache data BRAM organized as described above for each way
125 subtype cache_row_t is std_ulogic_vector(ROW_SIZE_BITS-1 downto 0);
127 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
128 -- not handle a clean (commented) definition of the cache tags as a 3d
129 -- memory. For now, work around it by putting all the tags
130 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
131 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
132 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
133 constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
134 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
135 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
137 -- The cache valid bits
138 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
139 type cache_valids_t is array(index_t) of cache_way_valids_t;
140 type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
142 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
143 signal cache_tags : cache_tags_array_t;
144 signal cache_valids : cache_valids_t;
146 attribute ram_style : string;
147 attribute ram_style of cache_tags : signal is "distributed";
148 attribute syn_ramstyle : string;
149 attribute syn_ramstyle of cache_tags : signal is "block_ram";
152 constant TLB_BITS : natural := log2(TLB_SIZE);
153 constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_BITS);
154 constant TLB_PTE_BITS : natural := 64;
156 subtype tlb_index_t is integer range 0 to TLB_SIZE - 1;
157 type tlb_valids_t is array(tlb_index_t) of std_ulogic;
158 subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
159 type tlb_tags_t is array(tlb_index_t) of tlb_tag_t;
160 subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
161 type tlb_ptes_t is array(tlb_index_t) of tlb_pte_t;
163 signal itlb_valids : tlb_valids_t;
164 signal itlb_tags : tlb_tags_t;
165 signal itlb_ptes : tlb_ptes_t;
166 attribute ram_style of itlb_tags : signal is "distributed";
167 attribute ram_style of itlb_ptes : signal is "distributed";
168 attribute syn_ramstyle of itlb_tags : signal is "block_ram";
169 attribute syn_ramstyle of itlb_ptes : signal is "block_ram";
171 -- Privilege bit from PTE EAA field
172 signal eaa_priv : std_ulogic;
174 -- Cache reload state machine
175 type state_t is (IDLE, CLR_TAG, WAIT_ACK);
177 type reg_internal_t is record
178 -- Cache hit state (Latches for 1 cycle BRAM access)
180 hit_nia : std_ulogic_vector(63 downto 0);
181 hit_smark : std_ulogic;
182 hit_valid : std_ulogic;
183 big_endian: std_ulogic;
185 -- Cache miss state (reload state machine)
187 wb : wishbone_master_out;
189 store_index : index_t;
191 store_tag : cache_tag_t;
192 store_valid : std_ulogic;
193 end_row_ix : row_in_line_t;
194 rows_valid : row_per_line_valid_t;
197 fetch_failed : std_ulogic;
200 signal r : reg_internal_t;
202 -- Async signals on incoming request
203 signal req_index : index_t;
204 signal req_row : row_t;
205 signal req_hit_way : way_t;
206 signal req_tag : cache_tag_t;
207 signal req_is_hit : std_ulogic;
208 signal req_is_miss : std_ulogic;
209 signal req_laddr : std_ulogic_vector(63 downto 0);
211 signal tlb_req_index : tlb_index_t;
212 signal real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
213 signal ra_valid : std_ulogic;
214 signal priv_fault : std_ulogic;
215 signal access_ok : std_ulogic;
216 signal use_previous : std_ulogic;
218 -- Cache RAM interface
219 type cache_ram_out_t is array(way_t) of cache_row_t;
220 signal cache_out : cache_ram_out_t;
222 -- PLRU output interface
223 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
224 signal plru_victim : plru_out_t;
225 signal replace_way : way_t;
227 -- Return the cache line index (tag index) for an address
228 function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
230 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
233 -- Return the cache row index (data memory) for an address
234 function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
236 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
239 -- Return the index of a row within a line
240 function get_row_of_line(row: row_t) return row_in_line_t is
241 variable row_v : unsigned(ROW_BITS-1 downto 0);
243 row_v := to_unsigned(row, ROW_BITS);
244 return row_v(ROW_LINEBITS-1 downto 0);
247 -- Returns whether this is the last row of a line
248 function is_last_row_addr(addr: wishbone_addr_type; last: row_in_line_t) return boolean is
250 return unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
253 -- Returns whether this is the last row of a line
254 function is_last_row(row: row_t; last: row_in_line_t) return boolean is
256 return get_row_of_line(row) = last;
259 -- Return the address of the next row in the current cache line
260 function next_row_addr(addr: wishbone_addr_type)
261 return std_ulogic_vector is
262 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
263 variable result : wishbone_addr_type;
265 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
266 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
267 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
269 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
273 -- Return the next row in the current cache line. We use a dedicated
274 -- function in order to limit the size of the generated adder to be
275 -- only the bits within a cache line (3 bits with default settings)
277 function next_row(row: row_t) return row_t is
278 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
279 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
280 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
282 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
283 row_idx := row_v(ROW_LINEBITS-1 downto 0);
284 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
285 return to_integer(unsigned(row_v));
288 -- Read the instruction word for the given address in the current cache row
289 function read_insn_word(addr: std_ulogic_vector(63 downto 0);
290 data: cache_row_t) return std_ulogic_vector is
291 variable word: integer range 0 to INSN_PER_ROW-1;
293 word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
294 return data(31+word*32 downto word*32);
297 -- Get the tag value from the address
298 function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
299 endian: std_ulogic) return cache_tag_t is
301 return endian & addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
304 -- Read a tag from a tag memory row
305 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
307 return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
310 -- Write a tag to tag memory row
311 procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
314 tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
317 -- Simple hash for direct-mapped TLB index
318 function hash_ea(addr: std_ulogic_vector(63 downto 0)) return tlb_index_t is
319 variable hash : std_ulogic_vector(TLB_BITS - 1 downto 0);
321 hash := addr(TLB_LG_PGSZ + TLB_BITS - 1 downto TLB_LG_PGSZ)
322 xor addr(TLB_LG_PGSZ + 2 * TLB_BITS - 1 downto TLB_LG_PGSZ + TLB_BITS)
323 xor addr(TLB_LG_PGSZ + 3 * TLB_BITS - 1 downto TLB_LG_PGSZ + 2 * TLB_BITS);
324 return to_integer(unsigned(hash));
328 assert LINE_SIZE mod ROW_SIZE = 0;
329 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
330 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
331 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
332 assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2" severity FAILURE;
333 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
334 report "geometry bits don't add up" severity FAILURE;
335 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
336 report "geometry bits don't add up" severity FAILURE;
337 assert (REAL_ADDR_BITS + 1 = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
338 report "geometry bits don't add up" severity FAILURE;
339 assert (REAL_ADDR_BITS + 1 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
340 report "geometry bits don't add up" severity FAILURE;
342 sim_debug: if SIM generate
345 report "ROW_SIZE = " & natural'image(ROW_SIZE);
346 report "ROW_PER_LINE = " & natural'image(ROW_PER_LINE);
347 report "BRAM_ROWS = " & natural'image(BRAM_ROWS);
348 report "INSN_PER_ROW = " & natural'image(INSN_PER_ROW);
349 report "INSN_BITS = " & natural'image(INSN_BITS);
350 report "ROW_BITS = " & natural'image(ROW_BITS);
351 report "ROW_LINEBITS = " & natural'image(ROW_LINEBITS);
352 report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
353 report "ROW_OFF_BITS = " & natural'image(ROW_OFF_BITS);
354 report "INDEX_BITS = " & natural'image(INDEX_BITS);
355 report "TAG_BITS = " & natural'image(TAG_BITS);
356 report "WAY_BITS = " & natural'image(WAY_BITS);
361 -- Generate a cache RAM for each way
362 rams: for i in 0 to NUM_WAYS-1 generate
363 signal do_read : std_ulogic;
364 signal do_write : std_ulogic;
365 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
366 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
367 signal dout : cache_row_t;
368 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
369 signal wr_dat : std_ulogic_vector(wishbone_in.dat'left downto 0);
371 way: entity work.cache_ram
373 ROW_BITS => ROW_BITS,
374 WIDTH => ROW_SIZE_BITS
388 -- byte-swap read data if big endian
389 if r.store_tag(TAG_BITS - 1) = '0' then
390 wr_dat <= wishbone_in.dat;
392 for ii in 0 to (wishbone_in.dat'length / 8) - 1 loop
393 j := ((ii / 4) * 4) + (3 - (ii mod 4));
394 wr_dat(ii * 8 + 7 downto ii * 8) <= wishbone_in.dat(j * 8 + 7 downto j * 8);
397 do_read <= not (stall_in or use_previous);
399 if wishbone_in.ack = '1' and replace_way = i then
402 cache_out(i) <= dout;
403 rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
404 wr_addr <= std_ulogic_vector(to_unsigned(r.store_row, ROW_BITS));
405 for ii in 0 to ROW_SIZE-1 loop
406 wr_sel(ii) <= do_write;
412 maybe_plrus: if NUM_WAYS > 1 generate
414 plrus: for i in 0 to NUM_LINES-1 generate
416 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
417 signal plru_acc_en : std_ulogic;
418 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
421 plru : entity work.plru
429 acc_en => plru_acc_en,
436 if get_index(r.hit_nia) = i then
437 plru_acc_en <= r.hit_valid;
441 plru_acc <= std_ulogic_vector(to_unsigned(r.hit_way, WAY_BITS));
442 plru_victim(i) <= plru_out;
447 -- TLB hit detection and real address generation
448 itlb_lookup : process(all)
449 variable pte : tlb_pte_t;
450 variable ttag : tlb_tag_t;
452 tlb_req_index <= hash_ea(i_in.nia);
453 pte := itlb_ptes(tlb_req_index);
454 ttag := itlb_tags(tlb_req_index);
455 if i_in.virt_mode = '1' then
456 real_addr <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
457 i_in.nia(TLB_LG_PGSZ - 1 downto 0);
458 if ttag = i_in.nia(63 downto TLB_LG_PGSZ + TLB_BITS) then
459 ra_valid <= itlb_valids(tlb_req_index);
465 real_addr <= i_in.nia(REAL_ADDR_BITS - 1 downto 0);
470 -- no IAMR, so no KUEP support for now
471 priv_fault <= eaa_priv and not i_in.priv_mode;
472 access_ok <= ra_valid and not priv_fault;
476 itlb_update: process(clk)
477 variable wr_index : tlb_index_t;
479 if rising_edge(clk) then
480 wr_index := hash_ea(m_in.addr);
481 if rst = '1' or (m_in.tlbie = '1' and m_in.doall = '1') then
482 -- clear all valid bits
483 for i in tlb_index_t loop
484 itlb_valids(i) <= '0';
486 elsif m_in.tlbie = '1' then
487 -- clear entry regardless of hit or miss
488 itlb_valids(wr_index) <= '0';
489 elsif m_in.tlbld = '1' then
490 itlb_tags(wr_index) <= m_in.addr(63 downto TLB_LG_PGSZ + TLB_BITS);
491 itlb_ptes(wr_index) <= m_in.pte;
492 itlb_valids(wr_index) <= '1';
497 -- Cache hit detection, output to fetch2 and other misc logic
498 icache_comb : process(all)
499 variable is_hit : std_ulogic;
500 variable hit_way : way_t;
502 -- i_in.sequential means that i_in.nia this cycle is 4 more than
503 -- last cycle. If we read more than 32 bits at a time, had a cache hit
504 -- last cycle, and we don't want the first 32-bit chunk, then we can
505 -- keep the data we read last cycle and just use that.
506 if unsigned(i_in.nia(INSN_BITS+2-1 downto 2)) /= 0 then
507 use_previous <= i_in.req and i_in.sequential and r.hit_valid;
512 -- Extract line, row and tag from request
513 req_index <= get_index(i_in.nia);
514 req_row <= get_row(i_in.nia);
515 req_tag <= get_tag(real_addr, i_in.big_endian);
517 -- Calculate address of beginning of cache row, will be
518 -- used for cache miss processing if needed
520 req_laddr <= (63 downto REAL_ADDR_BITS => '0') &
521 real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
522 (ROW_OFF_BITS-1 downto 0 => '0');
524 -- Test if pending request is a hit on any way
528 if i_in.req = '1' and
529 (cache_valids(req_index)(i) = '1' or
530 (r.state = WAIT_ACK and
531 req_index = r.store_index and
533 r.rows_valid(req_row mod ROW_PER_LINE) = '1')) then
534 if read_tag(i, cache_tags(req_index)) = req_tag then
541 -- Generate the "hit" and "miss" signals for the synchronous blocks
542 if i_in.req = '1' and access_ok = '1' and flush_in = '0' and rst = '0' then
543 req_is_hit <= is_hit;
544 req_is_miss <= not is_hit;
549 req_hit_way <= hit_way;
551 -- The way to replace on a miss
552 if r.state = CLR_TAG then
553 replace_way <= to_integer(unsigned(plru_victim(r.store_index)));
555 replace_way <= r.store_way;
558 -- Output instruction from current cache row
560 -- Note: This is a mild violation of our design principle of having pipeline
561 -- stages output from a clean latch. In this case we output the result
562 -- of a mux. The alternative would be output an entire row which
563 -- I prefer not to do just yet as it would force fetch2 to know about
564 -- some of the cache geometry information.
566 i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
567 i_out.valid <= r.hit_valid;
568 i_out.nia <= r.hit_nia;
569 i_out.stop_mark <= r.hit_smark;
570 i_out.fetch_failed <= r.fetch_failed;
571 i_out.big_endian <= r.big_endian;
572 i_out.next_predicted <= i_in.predicted;
574 -- Stall fetch1 if we have a miss on cache or TLB or a protection fault
575 stall_out <= not (is_hit and access_ok);
577 -- Wishbone requests output (from the cache miss reload machine)
578 wishbone_out <= r.wb;
581 -- Cache hit synchronous machine
582 icache_hit : process(clk)
584 if rising_edge(clk) then
585 -- keep outputs to fetch2 unchanged on a stall
586 -- except that flush or reset sets valid to 0
587 -- If use_previous, keep the same data as last cycle and use the second half
588 if stall_in = '1' or use_previous = '1' then
589 if rst = '1' or flush_in = '1' then
593 -- On a hit, latch the request for the next cycle, when the BRAM data
594 -- will be available on the cache_out output of the corresponding way
596 r.hit_valid <= req_is_hit;
597 if req_is_hit = '1' then
598 r.hit_way <= req_hit_way;
600 report "cache hit nia:" & to_hstring(i_in.nia) &
601 " IR:" & std_ulogic'image(i_in.virt_mode) &
602 " SM:" & std_ulogic'image(i_in.stop_mark) &
603 " idx:" & integer'image(req_index) &
604 " tag:" & to_hstring(req_tag) &
605 " way:" & integer'image(req_hit_way) &
606 " RA:" & to_hstring(real_addr);
609 if stall_in = '0' then
610 -- Send stop marks and NIA down regardless of validity
611 r.hit_smark <= i_in.stop_mark;
612 r.hit_nia <= i_in.nia;
613 r.big_endian <= i_in.big_endian;
618 -- Cache miss/reload synchronous machine
619 icache_miss : process(clk)
620 variable tagset : cache_tags_set_t;
621 variable stbs_done : boolean;
623 if rising_edge(clk) then
624 -- On reset, clear all valid bits to force misses
626 for i in index_t loop
627 cache_valids(i) <= (others => '0');
633 -- We only ever do reads on wishbone
634 r.wb.dat <= (others => '0');
635 r.wb.sel <= "11111111";
638 -- Not useful normally but helps avoiding tons of sim warnings
639 r.wb.adr <= (others => '0');
641 -- Process cache invalidations
642 if inval_in = '1' then
643 for i in index_t loop
644 cache_valids(i) <= (others => '0');
646 r.store_valid <= '0';
649 -- Main state machine
652 -- Reset per-row valid flags, only used in WAIT_ACK
653 for i in 0 to ROW_PER_LINE - 1 loop
654 r.rows_valid(i) <= '0';
657 -- We need to read a cache line
658 if req_is_miss = '1' then
659 report "cache miss nia:" & to_hstring(i_in.nia) &
660 " IR:" & std_ulogic'image(i_in.virt_mode) &
661 " SM:" & std_ulogic'image(i_in.stop_mark) &
662 " idx:" & integer'image(req_index) &
663 " way:" & integer'image(replace_way) &
664 " tag:" & to_hstring(req_tag) &
665 " RA:" & to_hstring(real_addr);
667 -- Keep track of our index and way for subsequent stores
668 r.store_index <= req_index;
669 r.store_row <= get_row(req_laddr);
670 r.store_tag <= req_tag;
671 r.store_valid <= '1';
672 r.end_row_ix <= get_row_of_line(get_row(req_laddr)) - 1;
674 -- Prep for first wishbone read. We calculate the address of
675 -- the start of the cache line and start the WB cycle.
677 r.wb.adr <= req_laddr(r.wb.adr'left downto 0);
681 -- Track that we had one request sent
685 when CLR_TAG | WAIT_ACK =>
686 if r.state = CLR_TAG then
687 -- Get victim way from plru
688 r.store_way <= replace_way;
690 -- Force misses on that way while reloading that line
691 cache_valids(req_index)(replace_way) <= '0';
693 -- Store new tag in selected way
694 for i in 0 to NUM_WAYS-1 loop
695 if i = replace_way then
696 tagset := cache_tags(r.store_index);
697 write_tag(i, tagset, r.store_tag);
698 cache_tags(r.store_index) <= tagset;
704 -- Requests are all sent if stb is 0
705 stbs_done := r.wb.stb = '0';
707 -- If we are still sending requests, was one accepted ?
708 if wishbone_in.stall = '0' and not stbs_done then
709 -- That was the last word ? We are done sending. Clear
710 -- stb and set stbs_done so we can handle an eventual last
711 -- ack on the same cycle.
713 if is_last_row_addr(r.wb.adr, r.end_row_ix) then
718 -- Calculate the next row address
719 r.wb.adr <= next_row_addr(r.wb.adr);
722 -- Incoming acks processing
723 if wishbone_in.ack = '1' then
724 r.rows_valid(r.store_row mod ROW_PER_LINE) <= '1';
725 -- Check for completion
726 if stbs_done and is_last_row(r.store_row, r.end_row_ix) then
727 -- Complete wishbone cycle
730 -- Cache line is now valid
731 cache_valids(r.store_index)(replace_way) <= r.store_valid and not inval_in;
737 -- Increment store row counter
738 r.store_row <= next_row(r.store_row);
743 -- TLB miss and protection fault processing
744 if rst = '1' or flush_in = '1' or m_in.tlbld = '1' then
745 r.fetch_failed <= '0';
746 elsif i_in.req = '1' and access_ok = '0' and stall_in = '0' then
747 r.fetch_failed <= '1';
752 icache_log: if LOG_LENGTH > 0 generate
753 -- Output data to logger
754 signal log_data : std_ulogic_vector(53 downto 0);
756 data_log: process(clk)
757 variable lway: way_t;
758 variable wstate: std_ulogic;
760 if rising_edge(clk) then
763 if r.state /= IDLE then
766 log_data <= i_out.valid &
769 r.wb.adr(5 downto 3) &
770 r.wb.stb & r.wb.cyc &
774 r.hit_nia(5 downto 2) &
776 std_ulogic_vector(to_unsigned(lway, 3)) &
777 req_is_hit & req_is_miss &