icache.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 -- 64 bit direct mapped icache. All instructions are 4B aligned.
  10
  11 entity icache is
  12     generic (
  13         -- Line size in bytes
  14         LINE_SIZE : natural := 64;
  15         -- Number of lines
  16         NUM_LINES : natural := 32
  17         );
  18     port (
  19         clk          : in std_ulogic;
  20         rst          : in std_ulogic;
  21
  22         i_in         : in Fetch1ToIcacheType;
  23         i_out        : out IcacheToFetch2Type;
  24
  25         stall_out    : out std_ulogic;
  26         flush_in     : in std_ulogic;
  27
  28         wishbone_out : out wishbone_master_out;
  29         wishbone_in  : in wishbone_slave_out
  30         );
  31 end entity icache;
  32
  33 architecture rtl of icache is
  34     function log2(i : natural) return integer is
  35         variable tmp : integer := i;
  36         variable ret : integer := 0;
  37     begin
  38         while tmp > 1 loop
  39             ret  := ret + 1;
  40             tmp := tmp / 2;
  41         end loop;
  42         return ret;
  43     end function;
  44
  45     function ispow2(i : integer) return boolean is
  46     begin
  47         if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then
  48             return true;
  49         else
  50             return false;
  51         end if;
  52     end function;
  53
  54     -- BRAM organisation: We never access more than wishbone_data_bits at
  55     -- a time so to save resources we make the array only that wide, and
  56     -- use consecutive indices for to make a cache "line"
  57     --
  58     -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
  59     constant ROW_SIZE      : natural := wishbone_data_bits / 8;
  60     -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
  61     constant ROW_PER_LINE  : natural := LINE_SIZE / ROW_SIZE;
  62     -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
  63     -- icache
  64     constant BRAM_ROWS     : natural := NUM_LINES * ROW_PER_LINE;
  65     -- INSN_PER_ROW is the number of 32bit instructions per BRAM row
  66     constant INSN_PER_ROW  : natural := wishbone_data_bits / 32;
  67     -- Bit fields counts in the address
  68
  69     -- INSN_BITS is the number of bits to select an instruction in a row
  70     constant INSN_BITS     : natural := log2(INSN_PER_ROW);
  71     -- ROW_BITS is the number of bits to select a row
  72     constant ROW_BITS      : natural := log2(BRAM_ROWS);
  73     -- ROW_LINEBITS is the number of bits to select a row within a line
  74     constant ROW_LINEBITS  : natural := log2(ROW_PER_LINE);
  75     -- LINE_OFF_BITS is the number of bits for the offset in a cache line
  76     constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
  77     -- ROW_OFF_BITS is the number of bits for the offset in a row
  78     constant ROW_OFF_BITS  : natural := log2(ROW_SIZE);
  79     -- INDEX_BITS is the number if bits to select a cache line
  80     constant INDEX_BITS    : natural := log2(NUM_LINES);
  81     -- TAG_BITS is the number of bits of the tag part of the address
  82     constant TAG_BITS      : natural := 64 - LINE_OFF_BITS - INDEX_BITS;
  83
  84     -- Example of layout for 32 lines of 64 bytes:
  85     --
  86     -- ..  tag    |index|  line  |
  87     -- ..         |   row   |    |
  88     -- ..         |     |   | |00| zero          (2)
  89     -- ..         |     |   |-|  | INSN_BITS     (1)
  90     -- ..         |     |---|    | ROW_LINEBITS  (3)
  91     -- ..         |     |--- - --| LINE_OFF_BITS (6)
  92     -- ..         |         |- --| ROW_OFF_BITS  (3)
  93     -- ..         |----- ---|    | ROW_BITS      (8)
  94     -- ..         |-----|        | INDEX_BITS    (5)
  95     -- .. --------|              | TAG_BITS      (53)
  96
  97     subtype row_t is integer range 0 to BRAM_ROWS-1;
  98     subtype index_t is integer range 0 to NUM_LINES-1;
  99
 100     -- The cache data BRAM organized as described above
 101     subtype cache_row_t is std_logic_vector(wishbone_data_bits-1 downto 0);
 102     type cache_array is array(row_t) of cache_row_t;
 103
 104     -- The cache tags LUTRAM has a row per cache line
 105     subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
 106     type cache_tags_array is array(index_t) of cache_tag_t;
 107
 108     -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
 109     signal cache_rows   : cache_array;
 110     signal tags         : cache_tags_array;
 111     signal tags_valid   : std_ulogic_vector(NUM_LINES-1 downto 0);
 112     attribute ram_style : string;
 113     attribute ram_style of cache_rows : signal is "block";
 114     attribute ram_decomp : string;
 115     attribute ram_decomp of cache_rows : signal is "power";
 116
 117     -- Cache reload state machine
 118     type state_t is (IDLE, WAIT_ACK);
 119
 120     type reg_internal_t is record
 121         -- Cache hit state (1 cycle BRAM access)
 122         hit_row   : cache_row_t;
 123         hit_nia   : std_ulogic_vector(63 downto 0);
 124         hit_smark : std_ulogic;
 125         hit_valid : std_ulogic;
 126
 127         -- Cache miss state (reload state machine)
 128         state            : state_t;
 129         wb               : wishbone_master_out;
 130         store_index      : index_t;
 131     end record;
 132
 133     signal r : reg_internal_t;
 134
 135     -- Async signals on incoming request
 136     signal req_index  : index_t;
 137     signal req_row    : row_t;
 138     signal req_tag    : cache_tag_t;
 139     signal req_is_hit : std_ulogic;
 140
 141     -- Return the cache line index (tag index) for an address
 142     function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
 143     begin
 144         return to_integer(unsigned(addr(63-TAG_BITS downto LINE_OFF_BITS)));
 145     end;
 146
 147     -- Return the cache row index (data memory) for an address
 148     function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
 149     begin
 150         return to_integer(unsigned(addr(63-TAG_BITS downto ROW_OFF_BITS)));
 151     end;
 152
 153     -- Returns whether this is the last row of a line
 154     function is_last_row(addr: std_ulogic_vector(63 downto 0)) return boolean is
 155         constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
 156     begin
 157         return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
 158     end;
 159
 160     -- Return the address of the next row in the current cache line
 161     function next_row_addr(addr: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
 162         variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
 163         variable result  : std_ulogic_vector(63 downto 0);
 164     begin
 165         -- Is there no simpler way in VHDL to generate that 3 bits adder ?
 166         row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
 167         row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
 168         result := addr;
 169         result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
 170         return result;
 171     end;
 172
 173     -- Read the instruction word for the given address in the current cache row
 174     function read_insn_word(addr: std_ulogic_vector(63 downto 0);
 175                             data: cache_row_t) return std_ulogic_vector is
 176         variable word: integer range 0 to INSN_PER_ROW-1;
 177     begin
 178         word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
 179         return data(31+word*32 downto word*32);
 180     end;
 181
 182     -- Get the tag value from the address
 183     function get_tag(addr: std_ulogic_vector(63 downto 0)) return cache_tag_t is
 184     begin
 185         return addr(63 downto 64-TAG_BITS);
 186     end;
 187
 188 begin
 189     assert ispow2(LINE_SIZE)    report "LINE_SIZE not power of 2" severity FAILURE;
 190     assert ispow2(NUM_LINES)    report "NUM_LINES not power of 2" severity FAILURE;
 191     assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
 192     assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2" severity FAILURE;
 193     assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
 194         report "geometry bits don't add up" severity FAILURE;
 195     assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
 196         report "geometry bits don't add up" severity FAILURE;
 197     assert (64 = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
 198         report "geometry bits don't add up" severity FAILURE;
 199     assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
 200         report "geometry bits don't add up" severity FAILURE;
 201
 202     debug: process
 203     begin
 204         report "ROW_SIZE      = " & natural'image(ROW_SIZE);
 205         report "ROW_PER_LINE  = " & natural'image(ROW_PER_LINE);
 206         report "BRAM_ROWS     = " & natural'image(BRAM_ROWS);
 207         report "INSN_PER_ROW  = " & natural'image(INSN_PER_ROW);
 208         report "INSN_BITS     = " & natural'image(INSN_BITS);
 209         report "ROW_BITS      = " & natural'image(ROW_BITS);
 210         report "ROW_LINEBITS  = " & natural'image(ROW_LINEBITS);
 211         report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
 212         report "ROW_OFF_BITS  = " & natural'image(ROW_OFF_BITS);
 213         report "INDEX_BITS    = " & natural'image(INDEX_BITS);
 214         report "TAG_BITS      = " & natural'image(TAG_BITS);
 215         wait;
 216     end process;
 217
 218     icache_comb : process(all)
 219     begin
 220         -- Extract line, row and tag from request
 221         req_index <= get_index(i_in.nia);
 222         req_row <= get_row(i_in.nia);
 223         req_tag <= get_tag(i_in.nia);
 224
 225         -- Test if pending request is a hit
 226         if tags(req_index) = req_tag then
 227             req_is_hit <= tags_valid(req_index);
 228         else
 229             req_is_hit <= '0';
 230         end if;
 231
 232         -- Output instruction from current cache row
 233         --
 234         -- Note: This is a mild violation of our design principle of having pipeline
 235         --       stages output from a clean latch. In this case we output the result
 236         --       of a mux. The alternative would be output an entire cache line
 237         --       which I prefer not to do just yet.
 238         --
 239         i_out.insn <= read_insn_word(r.hit_nia, r.hit_row);
 240         i_out.valid <= r.hit_valid;
 241         i_out.nia <= r.hit_nia;
 242         i_out.stop_mark <= r.hit_smark;
 243
 244         -- This needs to match the latching of a new request in process icache_hit
 245         stall_out <= not req_is_hit;
 246
 247         -- Wishbone requests output (from the cache miss reload machine)
 248         wishbone_out <= r.wb;
 249     end process;
 250
 251     icache_hit : process(clk)
 252     begin
 253         if rising_edge(clk) then
 254             -- Debug
 255             if i_in.req = '1' then
 256                 report "cache search for " & to_hstring(i_in.nia) &
 257                     " index:" & integer'image(req_index) &
 258                     " row:" & integer'image(req_row) &
 259                     " want_tag:" & to_hstring(req_tag) & " got_tag:" & to_hstring(req_tag) &
 260                     " valid:" & std_ulogic'image(tags_valid(req_index));
 261                 if req_is_hit = '1' then
 262                     report "is hit !";
 263                 else
 264                     report "is miss !";
 265                 end if;
 266             end if;
 267
 268             -- Are we free to latch a new request ?
 269             --
 270             -- Note: this test needs to match the equation for generating stall_out
 271             --
 272             if i_in.req = '1' and req_is_hit = '1' and flush_in = '0' then
 273                 -- Read the cache line (BRAM read port) and remember the NIA
 274                 r.hit_row <= cache_rows(req_row);
 275                 r.hit_nia <= i_in.nia;
 276                 r.hit_smark <= i_in.stop_mark;
 277                 r.hit_valid <= '1';
 278
 279                 report "cache hit nia:" & to_hstring(i_in.nia) &
 280                     " SM:" & std_ulogic'image(i_in.stop_mark) &
 281                     " idx:" & integer'image(req_index) &
 282                     " tag:" & to_hstring(req_tag);
 283             else
 284                 r.hit_valid <= '0';
 285                 -- Send stop marks down regardless of validity
 286                 r.hit_smark <= i_in.stop_mark;
 287             end if;
 288         end if;
 289     end process;
 290
 291     icache_miss : process(clk)
 292     begin
 293         if rising_edge(clk) then
 294             if rst = '1' then
 295                 tags_valid <= (others => '0');
 296                 r.state <= IDLE;
 297                 r.wb.cyc <= '0';
 298                 r.wb.stb <= '0';
 299
 300                 -- We only ever do reads on wishbone
 301                 r.wb.dat <= (others => '0');
 302                 r.wb.sel <= "11111111";
 303                 r.wb.we  <= '0';
 304             else
 305                 -- State machine
 306                 case r.state is
 307                 when IDLE =>
 308                     -- We need to read a cache line
 309                     if i_in.req = '1' and req_is_hit = '0' then
 310                         report "cache miss nia:" & to_hstring(i_in.nia) &
 311                             " SM:" & std_ulogic'image(i_in.stop_mark) &
 312                             " idx:" & integer'image(req_index) &
 313                             " tag:" & to_hstring(req_tag);
 314
 315                         -- Force misses while reloading that line
 316                         tags_valid(req_index) <= '0';
 317                         tags(req_index) <= req_tag;
 318                         r.store_index <= req_index;
 319
 320                         -- Prep for first wishbone read. We calculate the address off
 321                         -- the start of the cache line
 322                         r.wb.adr <= i_in.nia(63 downto LINE_OFF_BITS) &
 323                                     (LINE_OFF_BITS-1 downto 0 => '0');
 324                         r.wb.cyc <= '1';
 325                         r.wb.stb <= '1';
 326
 327                         r.state <= WAIT_ACK;
 328                     end if;
 329                 when WAIT_ACK =>
 330                     if wishbone_in.ack = '1' then
 331                         -- Store the current dword in both the cache
 332                         cache_rows(get_row(r.wb.adr)) <= wishbone_in.dat;
 333
 334                         -- That was the last word ? We are done
 335                         if is_last_row(r.wb.adr) then
 336                             tags_valid(r.store_index) <= '1';
 337                             r.wb.cyc <= '0';
 338                             r.wb.stb <= '0';
 339                             r.state <= IDLE;
 340                         else
 341                             -- Otherwise, calculate the next row address
 342                             r.wb.adr <= next_row_addr(r.wb.adr);
 343                         end if;
 344                     end if;
 345                 end case;
 346             end if;
 347         end if;
 348     end process;
 349 end;