icache_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity icache_tb is
   9 end icache_tb;
  10
  11 architecture behave of icache_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     signal i_out        : Fetch1ToIcacheType;
  16     signal i_in         : IcacheToFetch2Type;
  17
  18     signal wb_bram_in   : wishbone_master_out;
  19     signal wb_bram_out  : wishbone_slave_out;
  20
  21     constant clk_period : time := 10 ns;
  22 begin
  23     icache0: entity work.icache
  24         generic map(
  25             LINE_SIZE => 64,
  26             NUM_LINES => 4
  27             )
  28         port map(
  29             clk => clk,
  30             rst => rst,
  31             i_in => i_out,
  32             i_out => i_in,
  33             flush_in => '0',
  34             wishbone_out => wb_bram_in,
  35             wishbone_in => wb_bram_out
  36             );
  37
  38     -- BRAM Memory slave
  39     bram0: entity work.mw_soc_memory
  40         generic map(
  41             MEMORY_SIZE   => 128,
  42             RAM_INIT_FILE => "icache_test.bin"
  43             )
  44         port map(
  45             clk => clk,
  46             rst => rst,
  47             wishbone_in => wb_bram_in,
  48             wishbone_out => wb_bram_out
  49             );
  50
  51     clk_process: process
  52     begin
  53         clk <= '0';
  54         wait for clk_period/2;
  55         clk <= '1';
  56         wait for clk_period/2;
  57     end process;
  58
  59     rst_process: process
  60     begin
  61         rst <= '1';
  62         wait for 2*clk_period;
  63         rst <= '0';
  64         wait;
  65     end process;
  66
  67     stim: process
  68     begin
  69         i_out.req <= '0';
  70         i_out.nia <= (others => '0');
  71
  72         wait for 4*clk_period;
  73
  74         i_out.req <= '1';
  75         i_out.nia <= x"0000000000000004";
  76
  77         wait for 30*clk_period;
  78
  79         assert i_in.valid = '1';
  80         assert i_in.insn = x"00000001";
  81
  82         i_out.req <= '0';
  83
  84         wait for clk_period;
  85
  86         -- hit
  87         i_out.req <= '1';
  88         i_out.nia <= x"0000000000000008";
  89         wait for clk_period;
  90         assert i_in.valid = '1';
  91         assert i_in.insn = x"00000002";
  92         wait for clk_period;
  93
  94         -- another miss
  95         i_out.req <= '1';
  96         i_out.nia <= x"0000000000000040";
  97
  98         wait for 30*clk_period;
  99
 100         assert i_in.valid = '1';
 101         assert i_in.insn = x"00000010";
 102
 103         -- test something that aliases
 104         i_out.req <= '1';
 105         i_out.nia <= x"0000000000000100";
 106         wait for clk_period;
 107         assert i_in.valid = '0';
 108         wait for clk_period;
 109
 110         wait for 30*clk_period;
 111
 112         assert i_in.valid = '1';
 113         assert i_in.insn = x"00000040";
 114
 115         i_out.req <= '0';
 116
 117         assert false report "end of test" severity failure;
 118         wait;
 119
 120     end process;
 121 end;