include/ChangeLog

   1 2016-12-21  Alan Modra  <amodra@gmail.com>
   2
   3         * coff/pe.h: Fix comment chars with high bit set.
   4         * opcode/xgate.h: Likewise.
   5
   6 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
   7
   8         * opcode/mips.h (mips_opcode_32bit_p): New inline function.
   9
  10 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  11
  12         * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
  13         (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
  14         (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
  15         (EF_RISCV_FLOAT_ABI_QUAD): Define.
  16
  17 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  18             Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  19
  20         * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
  21
  22 2016-12-16  fincs  <fincs.alt1@gmail.com>
  23
  24         * bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
  25
  26 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  27
  28         * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
  29         typedef as `elf_internal_abiflags_v0'.
  30
  31 2016-12-13 Renlin Li <renlin.li@arm.com>
  32
  33         * opcode/aarch64.h (aarch64_operand_class): Remove
  34         AARCH64_OPND_CLASS_CP_REG.
  35         (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
  36         AARCH64_OPND_Cm to AARCH64_OPND_CRm.
  37         (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
  38
  39 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  40
  41         * opcode/mips.h: Remove references to `>' operand code.
  42
  43 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  44
  45         * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
  46
  47 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  48
  49         * opcode/mips.h (ASE_DSPR3): Add a comment.
  50
  51 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  52
  53         * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
  54         (ARM_ARCH_V8_3A): New.
  55
  56 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  57
  58         * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
  59         instruction classes.
  60
  61 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  62
  63         * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
  64         hwcaps2.
  65
  66 2016-11-22  Alan Modra  <amodra@gmail.com>
  67
  68         PR 20744
  69         * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
  70
  71 2016-11-03  David Tolnay <dtolnay@gmail.com>
  72             Mark Wielaard  <mark@klomp.org>
  73
  74         * demangle.h (DMGL_RUST): New macro.
  75         (DMGL_STYLE_MASK): Add DMGL_RUST.
  76         (demangling_styles): Add dlang_rust.
  77         (RUST_DEMANGLING_STYLE_STRING): New macro.
  78         (RUST_DEMANGLING): New macro.
  79         (rust_demangle): New prototype.
  80         (rust_is_mangled): Likewise.
  81         (rust_demangle_sym): Likewise.
  82
  83 2016-11-07  Jason Merrill  <jason@redhat.com>
  84
  85         * demangle.h (enum demangle_component_type): Add
  86         DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
  87
  88 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  89
  90         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
  91         AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
  92         (enum aarch64_op): Add OP_FCMLA_ELEM.
  93
  94 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  95
  96         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
  97         (enum aarch64_insn_class): Add ldst_imm10.
  98
  99 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 100
 101         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
 102
 103 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 104
 105         * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
 106         (AARCH64_ARCH_V8_3): Define.
 107         (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
 108
 109 2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 110
 111         * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
 112         (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
 113         (ARM_ARCH_V8M_MAIN_DSP): Likewise.
 114
 115 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 116
 117         * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
 118
 119 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 120
 121         * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
 122         fields.
 123         (struct arc_long_opcode): Delete.
 124         (struct arc_operand): Change types for insert and extract
 125         handlers.
 126
 127 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 128
 129         * opcode/arc.h: Make macros 64-bit safe.
 130
 131 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 132
 133         * opcode/arc.h (arc_opcode_len): Declare.
 134         (ARC_SHORT): Delete.
 135
 136 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 137             Andrew Waterman <andrew@sifive.com>
 138
 139         Add support for RISC-V architecture.
 140         * dis-asm.h: Add prototypes for print_insn_riscv and
 141         print_riscv_disassembler_options.
 142         * elf/riscv.h: New file.
 143         * opcode/riscv-opc.h: New file.
 144         * opcode/riscv.h: New file.
 145
 146 2016-10-17  Nick Clifton  <nickc@redhat.com>
 147
 148         * elf/common.h (DT_SYMTAB_SHNDX): Define.
 149         (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
 150         (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
 151         (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
 152         (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
 153         (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
 154         (ELFOSABI_OPENVOS): Define.
 155         (GRP_MASKOS, GRP_MASKPROC): Define.
 156
 157 2016-10-14  Pedro Alves  <palves@redhat.com>
 158
 159         * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
 160         OVERRIDE): Define as empty.
 161         [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
 162         __final.
 163         [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
 164         empty.
 165
 166 2016-10-14  Pedro Alves  <palves@redhat.com>
 167
 168         * ansidecl.h (GCC_FINAL): Delete.
 169         (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
 170
 171 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 172
 173         * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
 174
 175 2016-09-29  Alan Modra  <amodra@gmail.com>
 176
 177         * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
 178
 179 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 180
 181         * opcode/arc.h (insn_class_t): Add two new classes.
 182
 183 2016-09-26  Alan Modra  <amodra@gmail.com>
 184
 185         * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
 186
 187 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 188
 189         * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
 190
 191 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 192
 193         * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
 194         (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
 195         (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
 196         (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
 197
 198 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 199
 200         * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
 201         (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
 202         (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
 203         aarch64_insn_classes.
 204
 205 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 206
 207         * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
 208         (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
 209         (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
 210
 211 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 212
 213         * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
 214         (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
 215         (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
 216
 217 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 218
 219         * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
 220         (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
 221         (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
 222         (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
 223         (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
 224         (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
 225         (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
 226         (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
 227         (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
 228         (AARCH64_OPND_SVE_UIMM8_53): Likewise.
 229         (aarch64_sve_dupm_mov_immediate_p): Declare.
 230
 231 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 232
 233         * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
 234         (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
 235         (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
 236         (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
 237         (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
 238
 239 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 240
 241         * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
 242         (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
 243         (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
 244         (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
 245         (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
 246         (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
 247         (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
 248         (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
 249         (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
 250         (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
 251         (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
 252         (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
 253         (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
 254         (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
 255         (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
 256         (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
 257         Likewise.
 258
 259 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 260
 261         * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
 262         aarch64_opnd.
 263         (AARCH64_MOD_MUL): New aarch64_modifier_kind.
 264         (aarch64_opnd_info): Make shifter.amount an int64_t and
 265         rearrange the fields.
 266
 267 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 268
 269         * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
 270         (AARCH64_OPND_SVE_PRFOP): Likewise.
 271         (aarch64_sve_pattern_array): Declare.
 272         (aarch64_sve_prfop_array): Likewise.
 273
 274 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 275
 276         * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
 277         (AARCH64_OPND_QLF_P_M): Likewise.
 278
 279 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 280
 281         * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
 282         aarch64_operand_class.
 283         (AARCH64_OPND_CLASS_PRED_REG): Likewise.
 284         (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
 285         (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
 286         (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
 287         (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
 288         (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
 289         (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
 290         (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
 291
 292 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 293
 294         * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
 295         (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
 296
 297 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 298
 299         * opcode/aarch64.h (F_STRICT): New flag.
 300
 301 2016-09-07  Richard Earnshaw  <rearnsha@arm.com>
 302
 303         * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
 304
 305 2016-08-26  Cupertino Miranda  <cmiranda@synopsys.com>
 306         * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
 307         SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
 308         * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
 309         relocation.
 310
 311 2016-08-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 312
 313         * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
 314         (ARM_SET_SYM_CMSE_SPCL): Likewise.
 315
 316 2016-08-01  Andrew Jenner  <andrew@codesourcery.com>
 317
 318         * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
 319
 320 2016-07-29  Aldy Hernandez  <aldyh@redhat.com>
 321
 322         * libiberty.h (MAX_ALLOCA_SIZE): New macro.
 323
 324 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 325
 326         * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
 327         ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
 328         ARC_NUM_ADDRTYPES.
 329         * opcode/arc.h: Add BMU to insn_class_t enum.
 330         * opcode/arc.h: Add PMU to insn_class_t enum.
 331
 332 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 333
 334         * dis-asm.h: Declare print_arc_disassembler_options.
 335
 336 2016-07-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 337
 338         * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
 339         out_implib_bfd fields.
 340
 341 2016-07-14  Claudiu Zissulescu  <claziss@synopsys.com>
 342
 343         * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
 344
 345 2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>
 346
 347         * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
 348         (SHF_ARM_PURECODE): ... this.
 349
 350 2016-07-01  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 351
 352         * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
 353         (AARCH64_CPU_HAS_ANY_FEATURES): New.
 354         (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
 355         (AARCH64_OPCODE_HAS_FEATURE): Remove.
 356
 357 2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>
 358
 359         * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
 360         of enabled FPU features.
 361
 362 2016-06-29  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 363
 364         * opcode/sparc.h (enum sparc_opcode_arch_val): Move
 365         SPARC_OPCODE_ARCH_MAX into the enum.
 366
 367 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 368
 369         * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
 370
 371 2016-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 372
 373         * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
 374
 375 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 376
 377         * elf/xtensa.h (xtensa_make_property_section): New prototype.
 378
 379 2016-06-24  John Baldwin  <jhb@FreeBSD.org>
 380
 381         * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
 382         (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
 383         (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
 384         (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
 385
 386 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 387
 388         * opcode/arc.h: Make insn_class_t alphabetical again.
 389
 390 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 391
 392         * elf/dlx.h: Wrap in extern C.
 393         * elf/xtensa.h: Likewise.
 394         * opcode/arc.h: Likewise.
 395
 396 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 397
 398         * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
 399         tilegx_pipeline.
 400
 401 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 402
 403         * opcode/arc.h: Add nps400 extension and instruction
 404         subclass.
 405         Remove ARC_OPCODE_NPS400
 406         * elf/arc.h: Remove E_ARC_MACH_NPS400
 407
 408 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 409
 410         * opcode/sparc.h (enum sparc_opcode_arch_val): Add
 411         SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
 412         SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
 413         SPARC_OPCODE_ARCH_V9M.
 414
 415 2016-06-14  John Baldwin  <jhb@FreeBSD.org>
 416
 417         * opcode/msp430-decode.h (MSP430_Size): Remove.
 418         (Msp430_Opcode_Decoded): Change type of size to int.
 419
 420 2016-06-11  Alan Modra  <amodra@gmail.com>
 421
 422         * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
 423
 424 2016-06-08  Jose E. Marchesi  <jose.marchesi@oracle.com>
 425
 426         * opcode/sparc.h: Add missing documentation for hyperprivileged
 427         registers in rd (%) and rs1 ($).
 428
 429 2016-06-07  Alan Modra  <amodra@gmail.com>
 430
 431         * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
 432         PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
 433         PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
 434         PPC_APUINFO_VLE: Define.
 435
 436 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 437
 438         * opcode/arm.h (ARM_EXT2_RAS): New.  Also align preceding
 439         entries.
 440         (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
 441
 442 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 443
 444         * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
 445         (struct arc_long_opcode): New structure.
 446         (arc_long_opcodes): Declare.
 447         (arc_num_long_opcodes): Declare.
 448
 449 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 450
 451         * elf/mips.h: Add extern "C".
 452         * elf/sh.h: Likewise.
 453         * opcode/d10v.h: Likewise.
 454         * opcode/d30v.h: Likewise.
 455         * opcode/ia64.h: Likewise.
 456         * opcode/mips.h: Likewise.
 457         * opcode/ppc.h: Likewise.
 458         * opcode/sparc.h: Likewise.
 459         * opcode/tic6x.h: Likewise.
 460         * opcode/v850.h: Likewise.
 461
 462 2016-05-28  Alan Modra  <amodra@gmail.com>
 463
 464         * bfdlink.h (struct bfd_link_callbacks): Update comments.
 465         Return void from multiple_definition, multiple_common,
 466         add_to_set, constructor, warning, undefined_symbol,
 467         reloc_overflow, reloc_dangerous and unattached_reloc.
 468
 469 2016-05-26  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 470
 471         * opcode/metag.h: wrap declarations in extern "C".
 472
 473 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 474
 475         * opcode/arc.h (insn_subclass_t): Add COND.
 476         (flag_class_t): Add F_CLASS_EXTEND.
 477
 478 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 479
 480         * opcode/arc.h (struct arc_opcode): Renamed attribute class to
 481         insn_class.
 482         (struct arc_flag_class): Renamed attribute class to flag_class.
 483
 484 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 485
 486         * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
 487         plain symbol.
 488
 489 2016-04-29  Tom Tromey  <tom@tromey.com>
 490
 491         * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
 492         DW_LANG_Rust_old>: New constants.
 493
 494 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 495
 496         * elf/mips.h (AFL_ASE_DSPR3): New macro.
 497         (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
 498         * opcode/mips.h (ASE_DSPR3): New macro.
 499
 500 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 501             Nick Clifton  <nickc@redhat.com>
 502
 503         * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
 504         enumerator.
 505         (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
 506         (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
 507         (ARM_SYM_BRANCH_TYPE): Replace by ...
 508         (ARM_GET_SYM_BRANCH_TYPE): This and ...
 509         (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
 510         BFD_ASSERT is defined or not.
 511
 512 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 513
 514         * elf/arm.h (Tag_DSP_extension): Define.
 515
 516 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 517
 518         * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
 519
 520 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 521
 522         * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
 523         (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
 524         (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
 525         for the high core bits.
 526
 527 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 528
 529         * opcode/arc.h (ARC_SYNTAX_1OP): Declare
 530         (ARC_SYNTAX_NOP): Likewsie.
 531         (ARC_OP1_MUST_BE_IMM): Update defined value.
 532         (ARC_OP1_IMM_IMPLIED): Likewise.
 533         (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
 534
 535 2016-04-28  Nick Clifton  <nickc@redhat.com>
 536
 537         PR target/19722
 538         * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
 539
 540 2016-04-27  Alan Modra  <amodra@gmail.com>
 541
 542         * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
 543         undef.  Formatting.
 544
 545 2016-04-21  Nick Clifton  <nickc@redhat.com>
 546
 547         * bfdlink.h: Add prototype for bfd_link_check_relocs.
 548
 549 2016-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 550
 551         * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
 552
 553 2016-04-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 554
 555         * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
 556
 557 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 558
 559         * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
 560
 561 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 562
 563         * opcode/arc.h (insn_class_t): Add NET and ACL class.
 564
 565 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 566
 567         * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
 568         * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
 569
 570 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 571
 572         * opcode/arc.h (flag_class_t): Update.
 573         (ARC_OPCODE_NONE): Define.
 574         (ARC_OPCODE_ARCALL): Likewise.
 575         (ARC_OPCODE_ARCFPX): Likewise.
 576         (ARC_REGISTER_READONLY): Likewise.
 577         (ARC_REGISTER_WRITEONLY): Likewise.
 578         (ARC_REGISTER_NOSHORT_CUT): Likewise.
 579         (arc_aux_reg): Add cpu.
 580
 581 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 582
 583         * opcode/arc.h (arc_num_opcodes): Remove.
 584         (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
 585         (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
 586         (ARC_SUFFIX_FLAG): Define.
 587         (flags_none, flags_f, flags_cc, flags_ccf): Declare.
 588         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 589         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 590         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 591         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 592         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 593         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 594         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 595         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 596         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 597
 598 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 599
 600         * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
 601         (ARC_FPUDA): Define.
 602         (arc_aux_reg): Add new field.
 603
 604 2016-04-05  Cupertino Miranda  <cmiranda@synopsys.com>
 605
 606         * opcode/arc-func.h (replace_bits24): Changed.
 607         (replace_bits24_be): Created.
 608
 609 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 610
 611         * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
 612         (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
 613         (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
 614         (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
 615         (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
 616         (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
 617         (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
 618         (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
 619         (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
 620         (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
 621         (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
 622         (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
 623         (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
 624         (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
 625
 626 2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 627
 628         * opcode/i960.h: Add const qualifiers.
 629         * opcode/tic4x.h (struct tic4x_inst): Likewise.
 630
 631 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 632
 633         * opcodes/arc.h (insn_class_t): Add BITOP type.
 634
 635 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 636
 637         * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
 638         new classes instead.
 639
 640 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 641
 642         * elf/arc.h (E_ARC_MACH_NPS400): Define.
 643         * opcode/arc.h (ARC_OPCODE_NPS400): Define.
 644
 645 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 646
 647         * elf/arc.h (EF_ARC_CPU_GENERIC): Delete.  Update related comment.
 648
 649 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 650
 651         * elf/arc.h (EF_ARC_MACH): Delete.
 652         (EF_ARC_MACH_MSK): Remove out of date comment.
 653
 654 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 655
 656         * opcode/arc.h (ARC_OPCODE_BASE): Delete.
 657
 658 2016-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 659
 660         PR ld/19807
 661         * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
 662
 663 2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
 664             Andrew Burgess  <andrew.burgess@embecosm.com>
 665
 666         * elf/arc-reloc.def: Add a call to ME within the formula for each
 667         relocation that requires middle-endian correction.
 668
 669 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 670
 671         * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
 672         * opcode/h8300.h (struct h8_opcode): Likewise.
 673         * opcode/hppa.h (struct pa_opcode): Likewise.
 674         * opcode/msp430.h: Likewise.
 675         * opcode/spu.h (struct spu_opcode): Likewise.
 676         * opcode/tic30.h (struct _register): Likewise.
 677         * opcode/tic4x.h (struct tic4x_register): Likewise.
 678         (struct tic4x_cond): Likewise.
 679         (struct tic4x_indirect): Likewise.
 680         (struct tic4x_inst): Likewise.
 681         * opcode/visium.h (struct reg_entry): Likewise.
 682
 683 2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>
 684
 685         * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
 686         (ARM_CPU_HAS_FEATURE): Add comment.
 687
 688 2016-03-03  Than McIntosh <thanm@google.com>
 689
 690         * plugin-api.h: Add new hooks to the plugin transfer vector to
 691         to support querying section alignment and section size.
 692         (ld_plugin_get_input_section_alignment): New hook.
 693         (ld_plugin_get_input_section_size): New hook.
 694         (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
 695         and LDPT_GET_INPUT_SECTION_SIZE.
 696         (ld_plugin_tv): Add tv_get_input_section_alignment and
 697         tv_get_input_section_size.
 698
 699 2016-03-03  Evgenii Stepanov  <eugenis@google.com>
 700
 701         * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
 702
 703 2016-02-26  H.J. Lu  <hongjiu.lu@intel.com>
 704
 705         PR ld/19645
 706         * bfdlink.h (bfd_link_elf_stt_common): New enum.
 707         (bfd_link_info): Add elf_stt_common.
 708
 709 2016-02-26  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         PR ld/19636
 712         PR ld/19704
 713         PR ld/19719
 714         * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
 715
 716 2016-02-19  Matthew Wahab  <matthew.wahab@arm.com>
 717             Jiong Wang  <jiong.wang@arm.com>
 718
 719         * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
 720
 721 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 722             Janek van Oirschot  <jvanoirs@synopsys.com>
 723
 724         * opcode/arc.h (arc_opcode arc_relax_opcodes)
 725         (arc_num_relax_opcodes): Declare.
 726
 727 2016-02-09  Nick Clifton  <nickc@redhat.com>
 728
 729         * opcode/metag.h (metag_scondtab): Mark as possibly unused.
 730         * opcode/nds32.h (nds32_r45map): Likewise.
 731         (nds32_r54map): Likewise.
 732         * opcode/visium.h (gen_reg_table): Likewise.
 733         (fp_reg_table, cc_table, opcode_table): Likewise.
 734
 735 2016-02-09  Alan Modra  <amodra@gmail.com>
 736
 737         PR 16583
 738         * elf/common.h (AT_SUN_HWCAP): Undef before defining.
 739
 740 2016-02-04  Nick Clifton  <nickc@redhat.com>
 741
 742         PR target/19561
 743         * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
 744         (RRUX): Synthesise using case 2 rather than 7.
 745
 746 2016-01-19  John Baldwin  <jhb@FreeBSD.org>
 747
 748         * elf/common.h (NT_FREEBSD_THRMISC): Define.
 749         (NT_FREEBSD_PROCSTAT_PROC): Define.
 750         (NT_FREEBSD_PROCSTAT_FILES): Define.
 751         (NT_FREEBSD_PROCSTAT_VMMAP): Define.
 752         (NT_FREEBSD_PROCSTAT_GROUPS): Define.
 753         (NT_FREEBSD_PROCSTAT_UMASK): Define.
 754         (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
 755         (NT_FREEBSD_PROCSTAT_OSREL): Define.
 756         (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
 757         (NT_FREEBSD_PROCSTAT_AUXV): Define.
 758
 759 2016-01-18  Miranda Cupertino  <Cupertino.Miranda@synopsys.com>
 760             Zissulescu Claudiu  <Claudiu.Zissulescu@synopsys.com>
 761
 762         * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
 763         (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
 764         (ARC_TLS_LE_32): Fixed formula.
 765         (ARC_TLS_GD_LD): Use new special function.
 766         * opcode/arc-func.h: Changed all the replacement
 767         functions to clear the patching bits before doing an or it with the value
 768         argument.
 769
 770 2016-01-18  Nick Clifton  <nickc@redhat.com>
 771
 772         PR ld/19440
 773         * coff/internal.h (internal_syment): Use int to hold section
 774         number.
 775         (N_UNDEF): Cast to int not short.
 776         (N_ABS): Likewise.
 777         (N_DEBUG): Likewise.
 778         (N_TV): Likewise.
 779         (P_TV): Likewise.
 780
 781 2016-01-11  Nick Clifton  <nickc@redhat.com>
 782
 783         Import this change from GCC mainline:
 784
 785         2016-01-07  Mike Frysinger  <vapier@gentoo.org>
 786
 787         * longlong.h: Change !__SHMEDIA__ to
 788         (!defined (__SHMEDIA__) || !__SHMEDIA__).
 789         Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
 790
 791 2016-01-06  Maciej W. Rozycki  <macro@imgtec.com>
 792
 793         * opcode/mips.h: Add a summary of MIPS16 operand codes.
 794
 795 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 796
 797         * libiberty.h (dupargv): Change arg to char * const *.
 798         (writeargv, countargv): Likewise.
 799
 800 2016-01-01  Alan Modra  <amodra@gmail.com>
 801
 802         Update year range in copyright notice of all files.
 803
 804 For older changes see ChangeLog-0415, aout/ChangeLog-9115,
 805 cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
 806 mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
 807 som/ChangeLog-1015, and vms/ChangeLog-1015
 808 \f
 809 Copyright (C) 2016 Free Software Foundation, Inc.
 810
 811 Copying and distribution of this file, with or without modification,
 812 are permitted in any medium without royalty provided the copyright
 813 notice and this notice are preserved.
 814
 815 Local Variables:
 816 mode: change-log
 817 left-margin: 8
 818 fill-column: 74
 819 version-control: never
 820 End: