include/ChangeLog

   1 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
   4         operand codes.
   5
   6 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
   7
   8         * opcode/mips.h: Replace `0' and `4' operand codes with `.' and
   9         `F' respectively.
  10
  11 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  12
  13         * opcode/mips.h (INSN2_SHORT_ONLY): New macro.
  14
  15 2016-12-21  Alan Modra  <amodra@gmail.com>
  16
  17         * coff/pe.h: Fix comment chars with high bit set.
  18         * opcode/xgate.h: Likewise.
  19
  20 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  21
  22         * opcode/mips.h (mips_opcode_32bit_p): New inline function.
  23
  24 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  25
  26         * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
  27         (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
  28         (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
  29         (EF_RISCV_FLOAT_ABI_QUAD): Define.
  30
  31 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  32             Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  33
  34         * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
  35
  36 2016-12-16  fincs  <fincs.alt1@gmail.com>
  37
  38         * bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
  39
  40 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  41
  42         * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
  43         typedef as `elf_internal_abiflags_v0'.
  44
  45 2016-12-13 Renlin Li <renlin.li@arm.com>
  46
  47         * opcode/aarch64.h (aarch64_operand_class): Remove
  48         AARCH64_OPND_CLASS_CP_REG.
  49         (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
  50         AARCH64_OPND_Cm to AARCH64_OPND_CRm.
  51         (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
  52
  53 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  54
  55         * opcode/mips.h: Remove references to `>' operand code.
  56
  57 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  58
  59         * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
  60
  61 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  62
  63         * opcode/mips.h (ASE_DSPR3): Add a comment.
  64
  65 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  66
  67         * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
  68         (ARM_ARCH_V8_3A): New.
  69
  70 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  71
  72         * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
  73         instruction classes.
  74
  75 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  76
  77         * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
  78         hwcaps2.
  79
  80 2016-11-22  Alan Modra  <amodra@gmail.com>
  81
  82         PR 20744
  83         * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
  84
  85 2016-11-03  David Tolnay <dtolnay@gmail.com>
  86             Mark Wielaard  <mark@klomp.org>
  87
  88         * demangle.h (DMGL_RUST): New macro.
  89         (DMGL_STYLE_MASK): Add DMGL_RUST.
  90         (demangling_styles): Add dlang_rust.
  91         (RUST_DEMANGLING_STYLE_STRING): New macro.
  92         (RUST_DEMANGLING): New macro.
  93         (rust_demangle): New prototype.
  94         (rust_is_mangled): Likewise.
  95         (rust_demangle_sym): Likewise.
  96
  97 2016-11-07  Jason Merrill  <jason@redhat.com>
  98
  99         * demangle.h (enum demangle_component_type): Add
 100         DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
 101
 102 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 103
 104         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
 105         AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
 106         (enum aarch64_op): Add OP_FCMLA_ELEM.
 107
 108 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 109
 110         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
 111         (enum aarch64_insn_class): Add ldst_imm10.
 112
 113 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 114
 115         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
 116
 117 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 118
 119         * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
 120         (AARCH64_ARCH_V8_3): Define.
 121         (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
 122
 123 2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 124
 125         * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
 126         (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
 127         (ARM_ARCH_V8M_MAIN_DSP): Likewise.
 128
 129 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 130
 131         * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
 132
 133 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 134
 135         * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
 136         fields.
 137         (struct arc_long_opcode): Delete.
 138         (struct arc_operand): Change types for insert and extract
 139         handlers.
 140
 141 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 142
 143         * opcode/arc.h: Make macros 64-bit safe.
 144
 145 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 146
 147         * opcode/arc.h (arc_opcode_len): Declare.
 148         (ARC_SHORT): Delete.
 149
 150 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 151             Andrew Waterman <andrew@sifive.com>
 152
 153         Add support for RISC-V architecture.
 154         * dis-asm.h: Add prototypes for print_insn_riscv and
 155         print_riscv_disassembler_options.
 156         * elf/riscv.h: New file.
 157         * opcode/riscv-opc.h: New file.
 158         * opcode/riscv.h: New file.
 159
 160 2016-10-17  Nick Clifton  <nickc@redhat.com>
 161
 162         * elf/common.h (DT_SYMTAB_SHNDX): Define.
 163         (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
 164         (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
 165         (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
 166         (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
 167         (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
 168         (ELFOSABI_OPENVOS): Define.
 169         (GRP_MASKOS, GRP_MASKPROC): Define.
 170
 171 2016-10-14  Pedro Alves  <palves@redhat.com>
 172
 173         * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
 174         OVERRIDE): Define as empty.
 175         [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
 176         __final.
 177         [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
 178         empty.
 179
 180 2016-10-14  Pedro Alves  <palves@redhat.com>
 181
 182         * ansidecl.h (GCC_FINAL): Delete.
 183         (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
 184
 185 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 186
 187         * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
 188
 189 2016-09-29  Alan Modra  <amodra@gmail.com>
 190
 191         * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
 192
 193 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 194
 195         * opcode/arc.h (insn_class_t): Add two new classes.
 196
 197 2016-09-26  Alan Modra  <amodra@gmail.com>
 198
 199         * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
 200
 201 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 202
 203         * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
 204
 205 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 206
 207         * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
 208         (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
 209         (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
 210         (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
 211
 212 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 213
 214         * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
 215         (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
 216         (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
 217         aarch64_insn_classes.
 218
 219 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 220
 221         * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
 222         (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
 223         (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
 224
 225 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 226
 227         * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
 228         (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
 229         (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
 230
 231 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 232
 233         * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
 234         (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
 235         (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
 236         (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
 237         (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
 238         (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
 239         (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
 240         (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
 241         (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
 242         (AARCH64_OPND_SVE_UIMM8_53): Likewise.
 243         (aarch64_sve_dupm_mov_immediate_p): Declare.
 244
 245 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 246
 247         * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
 248         (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
 249         (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
 250         (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
 251         (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
 252
 253 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 254
 255         * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
 256         (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
 257         (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
 258         (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
 259         (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
 260         (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
 261         (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
 262         (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
 263         (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
 264         (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
 265         (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
 266         (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
 267         (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
 268         (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
 269         (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
 270         (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
 271         Likewise.
 272
 273 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 274
 275         * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
 276         aarch64_opnd.
 277         (AARCH64_MOD_MUL): New aarch64_modifier_kind.
 278         (aarch64_opnd_info): Make shifter.amount an int64_t and
 279         rearrange the fields.
 280
 281 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 282
 283         * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
 284         (AARCH64_OPND_SVE_PRFOP): Likewise.
 285         (aarch64_sve_pattern_array): Declare.
 286         (aarch64_sve_prfop_array): Likewise.
 287
 288 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 289
 290         * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
 291         (AARCH64_OPND_QLF_P_M): Likewise.
 292
 293 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 294
 295         * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
 296         aarch64_operand_class.
 297         (AARCH64_OPND_CLASS_PRED_REG): Likewise.
 298         (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
 299         (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
 300         (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
 301         (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
 302         (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
 303         (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
 304         (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
 305
 306 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 307
 308         * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
 309         (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
 310
 311 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 312
 313         * opcode/aarch64.h (F_STRICT): New flag.
 314
 315 2016-09-07  Richard Earnshaw  <rearnsha@arm.com>
 316
 317         * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
 318
 319 2016-08-26  Cupertino Miranda  <cmiranda@synopsys.com>
 320         * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
 321         SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
 322         * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
 323         relocation.
 324
 325 2016-08-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 326
 327         * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
 328         (ARM_SET_SYM_CMSE_SPCL): Likewise.
 329
 330 2016-08-01  Andrew Jenner  <andrew@codesourcery.com>
 331
 332         * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
 333
 334 2016-07-29  Aldy Hernandez  <aldyh@redhat.com>
 335
 336         * libiberty.h (MAX_ALLOCA_SIZE): New macro.
 337
 338 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 339
 340         * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
 341         ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
 342         ARC_NUM_ADDRTYPES.
 343         * opcode/arc.h: Add BMU to insn_class_t enum.
 344         * opcode/arc.h: Add PMU to insn_class_t enum.
 345
 346 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 347
 348         * dis-asm.h: Declare print_arc_disassembler_options.
 349
 350 2016-07-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 351
 352         * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
 353         out_implib_bfd fields.
 354
 355 2016-07-14  Claudiu Zissulescu  <claziss@synopsys.com>
 356
 357         * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
 358
 359 2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>
 360
 361         * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
 362         (SHF_ARM_PURECODE): ... this.
 363
 364 2016-07-01  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 365
 366         * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
 367         (AARCH64_CPU_HAS_ANY_FEATURES): New.
 368         (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
 369         (AARCH64_OPCODE_HAS_FEATURE): Remove.
 370
 371 2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>
 372
 373         * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
 374         of enabled FPU features.
 375
 376 2016-06-29  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 377
 378         * opcode/sparc.h (enum sparc_opcode_arch_val): Move
 379         SPARC_OPCODE_ARCH_MAX into the enum.
 380
 381 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 382
 383         * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
 384
 385 2016-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 386
 387         * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
 388
 389 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 390
 391         * elf/xtensa.h (xtensa_make_property_section): New prototype.
 392
 393 2016-06-24  John Baldwin  <jhb@FreeBSD.org>
 394
 395         * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
 396         (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
 397         (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
 398         (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
 399
 400 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 401
 402         * opcode/arc.h: Make insn_class_t alphabetical again.
 403
 404 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 405
 406         * elf/dlx.h: Wrap in extern C.
 407         * elf/xtensa.h: Likewise.
 408         * opcode/arc.h: Likewise.
 409
 410 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 411
 412         * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
 413         tilegx_pipeline.
 414
 415 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 416
 417         * opcode/arc.h: Add nps400 extension and instruction
 418         subclass.
 419         Remove ARC_OPCODE_NPS400
 420         * elf/arc.h: Remove E_ARC_MACH_NPS400
 421
 422 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 423
 424         * opcode/sparc.h (enum sparc_opcode_arch_val): Add
 425         SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
 426         SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
 427         SPARC_OPCODE_ARCH_V9M.
 428
 429 2016-06-14  John Baldwin  <jhb@FreeBSD.org>
 430
 431         * opcode/msp430-decode.h (MSP430_Size): Remove.
 432         (Msp430_Opcode_Decoded): Change type of size to int.
 433
 434 2016-06-11  Alan Modra  <amodra@gmail.com>
 435
 436         * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
 437
 438 2016-06-08  Jose E. Marchesi  <jose.marchesi@oracle.com>
 439
 440         * opcode/sparc.h: Add missing documentation for hyperprivileged
 441         registers in rd (%) and rs1 ($).
 442
 443 2016-06-07  Alan Modra  <amodra@gmail.com>
 444
 445         * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
 446         PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
 447         PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
 448         PPC_APUINFO_VLE: Define.
 449
 450 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 451
 452         * opcode/arm.h (ARM_EXT2_RAS): New.  Also align preceding
 453         entries.
 454         (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
 455
 456 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 457
 458         * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
 459         (struct arc_long_opcode): New structure.
 460         (arc_long_opcodes): Declare.
 461         (arc_num_long_opcodes): Declare.
 462
 463 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 464
 465         * elf/mips.h: Add extern "C".
 466         * elf/sh.h: Likewise.
 467         * opcode/d10v.h: Likewise.
 468         * opcode/d30v.h: Likewise.
 469         * opcode/ia64.h: Likewise.
 470         * opcode/mips.h: Likewise.
 471         * opcode/ppc.h: Likewise.
 472         * opcode/sparc.h: Likewise.
 473         * opcode/tic6x.h: Likewise.
 474         * opcode/v850.h: Likewise.
 475
 476 2016-05-28  Alan Modra  <amodra@gmail.com>
 477
 478         * bfdlink.h (struct bfd_link_callbacks): Update comments.
 479         Return void from multiple_definition, multiple_common,
 480         add_to_set, constructor, warning, undefined_symbol,
 481         reloc_overflow, reloc_dangerous and unattached_reloc.
 482
 483 2016-05-26  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 484
 485         * opcode/metag.h: wrap declarations in extern "C".
 486
 487 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 488
 489         * opcode/arc.h (insn_subclass_t): Add COND.
 490         (flag_class_t): Add F_CLASS_EXTEND.
 491
 492 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 493
 494         * opcode/arc.h (struct arc_opcode): Renamed attribute class to
 495         insn_class.
 496         (struct arc_flag_class): Renamed attribute class to flag_class.
 497
 498 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 499
 500         * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
 501         plain symbol.
 502
 503 2016-04-29  Tom Tromey  <tom@tromey.com>
 504
 505         * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
 506         DW_LANG_Rust_old>: New constants.
 507
 508 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 509
 510         * elf/mips.h (AFL_ASE_DSPR3): New macro.
 511         (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
 512         * opcode/mips.h (ASE_DSPR3): New macro.
 513
 514 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 515             Nick Clifton  <nickc@redhat.com>
 516
 517         * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
 518         enumerator.
 519         (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
 520         (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
 521         (ARM_SYM_BRANCH_TYPE): Replace by ...
 522         (ARM_GET_SYM_BRANCH_TYPE): This and ...
 523         (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
 524         BFD_ASSERT is defined or not.
 525
 526 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 527
 528         * elf/arm.h (Tag_DSP_extension): Define.
 529
 530 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 531
 532         * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
 533
 534 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 535
 536         * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
 537         (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
 538         (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
 539         for the high core bits.
 540
 541 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 542
 543         * opcode/arc.h (ARC_SYNTAX_1OP): Declare
 544         (ARC_SYNTAX_NOP): Likewsie.
 545         (ARC_OP1_MUST_BE_IMM): Update defined value.
 546         (ARC_OP1_IMM_IMPLIED): Likewise.
 547         (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
 548
 549 2016-04-28  Nick Clifton  <nickc@redhat.com>
 550
 551         PR target/19722
 552         * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
 553
 554 2016-04-27  Alan Modra  <amodra@gmail.com>
 555
 556         * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
 557         undef.  Formatting.
 558
 559 2016-04-21  Nick Clifton  <nickc@redhat.com>
 560
 561         * bfdlink.h: Add prototype for bfd_link_check_relocs.
 562
 563 2016-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 564
 565         * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
 566
 567 2016-04-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 568
 569         * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
 570
 571 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 572
 573         * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
 574
 575 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 576
 577         * opcode/arc.h (insn_class_t): Add NET and ACL class.
 578
 579 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 580
 581         * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
 582         * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
 583
 584 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 585
 586         * opcode/arc.h (flag_class_t): Update.
 587         (ARC_OPCODE_NONE): Define.
 588         (ARC_OPCODE_ARCALL): Likewise.
 589         (ARC_OPCODE_ARCFPX): Likewise.
 590         (ARC_REGISTER_READONLY): Likewise.
 591         (ARC_REGISTER_WRITEONLY): Likewise.
 592         (ARC_REGISTER_NOSHORT_CUT): Likewise.
 593         (arc_aux_reg): Add cpu.
 594
 595 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 596
 597         * opcode/arc.h (arc_num_opcodes): Remove.
 598         (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
 599         (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
 600         (ARC_SUFFIX_FLAG): Define.
 601         (flags_none, flags_f, flags_cc, flags_ccf): Declare.
 602         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 603         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 604         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 605         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 606         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 607         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 608         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 609         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 610         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 611
 612 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 613
 614         * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
 615         (ARC_FPUDA): Define.
 616         (arc_aux_reg): Add new field.
 617
 618 2016-04-05  Cupertino Miranda  <cmiranda@synopsys.com>
 619
 620         * opcode/arc-func.h (replace_bits24): Changed.
 621         (replace_bits24_be): Created.
 622
 623 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 624
 625         * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
 626         (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
 627         (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
 628         (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
 629         (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
 630         (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
 631         (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
 632         (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
 633         (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
 634         (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
 635         (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
 636         (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
 637         (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
 638         (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
 639
 640 2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 641
 642         * opcode/i960.h: Add const qualifiers.
 643         * opcode/tic4x.h (struct tic4x_inst): Likewise.
 644
 645 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 646
 647         * opcodes/arc.h (insn_class_t): Add BITOP type.
 648
 649 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 650
 651         * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
 652         new classes instead.
 653
 654 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 655
 656         * elf/arc.h (E_ARC_MACH_NPS400): Define.
 657         * opcode/arc.h (ARC_OPCODE_NPS400): Define.
 658
 659 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 660
 661         * elf/arc.h (EF_ARC_CPU_GENERIC): Delete.  Update related comment.
 662
 663 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 664
 665         * elf/arc.h (EF_ARC_MACH): Delete.
 666         (EF_ARC_MACH_MSK): Remove out of date comment.
 667
 668 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 669
 670         * opcode/arc.h (ARC_OPCODE_BASE): Delete.
 671
 672 2016-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 673
 674         PR ld/19807
 675         * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
 676
 677 2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
 678             Andrew Burgess  <andrew.burgess@embecosm.com>
 679
 680         * elf/arc-reloc.def: Add a call to ME within the formula for each
 681         relocation that requires middle-endian correction.
 682
 683 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 684
 685         * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
 686         * opcode/h8300.h (struct h8_opcode): Likewise.
 687         * opcode/hppa.h (struct pa_opcode): Likewise.
 688         * opcode/msp430.h: Likewise.
 689         * opcode/spu.h (struct spu_opcode): Likewise.
 690         * opcode/tic30.h (struct _register): Likewise.
 691         * opcode/tic4x.h (struct tic4x_register): Likewise.
 692         (struct tic4x_cond): Likewise.
 693         (struct tic4x_indirect): Likewise.
 694         (struct tic4x_inst): Likewise.
 695         * opcode/visium.h (struct reg_entry): Likewise.
 696
 697 2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>
 698
 699         * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
 700         (ARM_CPU_HAS_FEATURE): Add comment.
 701
 702 2016-03-03  Than McIntosh <thanm@google.com>
 703
 704         * plugin-api.h: Add new hooks to the plugin transfer vector to
 705         to support querying section alignment and section size.
 706         (ld_plugin_get_input_section_alignment): New hook.
 707         (ld_plugin_get_input_section_size): New hook.
 708         (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
 709         and LDPT_GET_INPUT_SECTION_SIZE.
 710         (ld_plugin_tv): Add tv_get_input_section_alignment and
 711         tv_get_input_section_size.
 712
 713 2016-03-03  Evgenii Stepanov  <eugenis@google.com>
 714
 715         * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
 716
 717 2016-02-26  H.J. Lu  <hongjiu.lu@intel.com>
 718
 719         PR ld/19645
 720         * bfdlink.h (bfd_link_elf_stt_common): New enum.
 721         (bfd_link_info): Add elf_stt_common.
 722
 723 2016-02-26  H.J. Lu  <hongjiu.lu@intel.com>
 724
 725         PR ld/19636
 726         PR ld/19704
 727         PR ld/19719
 728         * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
 729
 730 2016-02-19  Matthew Wahab  <matthew.wahab@arm.com>
 731             Jiong Wang  <jiong.wang@arm.com>
 732
 733         * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
 734
 735 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 736             Janek van Oirschot  <jvanoirs@synopsys.com>
 737
 738         * opcode/arc.h (arc_opcode arc_relax_opcodes)
 739         (arc_num_relax_opcodes): Declare.
 740
 741 2016-02-09  Nick Clifton  <nickc@redhat.com>
 742
 743         * opcode/metag.h (metag_scondtab): Mark as possibly unused.
 744         * opcode/nds32.h (nds32_r45map): Likewise.
 745         (nds32_r54map): Likewise.
 746         * opcode/visium.h (gen_reg_table): Likewise.
 747         (fp_reg_table, cc_table, opcode_table): Likewise.
 748
 749 2016-02-09  Alan Modra  <amodra@gmail.com>
 750
 751         PR 16583
 752         * elf/common.h (AT_SUN_HWCAP): Undef before defining.
 753
 754 2016-02-04  Nick Clifton  <nickc@redhat.com>
 755
 756         PR target/19561
 757         * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
 758         (RRUX): Synthesise using case 2 rather than 7.
 759
 760 2016-01-19  John Baldwin  <jhb@FreeBSD.org>
 761
 762         * elf/common.h (NT_FREEBSD_THRMISC): Define.
 763         (NT_FREEBSD_PROCSTAT_PROC): Define.
 764         (NT_FREEBSD_PROCSTAT_FILES): Define.
 765         (NT_FREEBSD_PROCSTAT_VMMAP): Define.
 766         (NT_FREEBSD_PROCSTAT_GROUPS): Define.
 767         (NT_FREEBSD_PROCSTAT_UMASK): Define.
 768         (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
 769         (NT_FREEBSD_PROCSTAT_OSREL): Define.
 770         (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
 771         (NT_FREEBSD_PROCSTAT_AUXV): Define.
 772
 773 2016-01-18  Miranda Cupertino  <Cupertino.Miranda@synopsys.com>
 774             Zissulescu Claudiu  <Claudiu.Zissulescu@synopsys.com>
 775
 776         * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
 777         (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
 778         (ARC_TLS_LE_32): Fixed formula.
 779         (ARC_TLS_GD_LD): Use new special function.
 780         * opcode/arc-func.h: Changed all the replacement
 781         functions to clear the patching bits before doing an or it with the value
 782         argument.
 783
 784 2016-01-18  Nick Clifton  <nickc@redhat.com>
 785
 786         PR ld/19440
 787         * coff/internal.h (internal_syment): Use int to hold section
 788         number.
 789         (N_UNDEF): Cast to int not short.
 790         (N_ABS): Likewise.
 791         (N_DEBUG): Likewise.
 792         (N_TV): Likewise.
 793         (P_TV): Likewise.
 794
 795 2016-01-11  Nick Clifton  <nickc@redhat.com>
 796
 797         Import this change from GCC mainline:
 798
 799         2016-01-07  Mike Frysinger  <vapier@gentoo.org>
 800
 801         * longlong.h: Change !__SHMEDIA__ to
 802         (!defined (__SHMEDIA__) || !__SHMEDIA__).
 803         Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
 804
 805 2016-01-06  Maciej W. Rozycki  <macro@imgtec.com>
 806
 807         * opcode/mips.h: Add a summary of MIPS16 operand codes.
 808
 809 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 810
 811         * libiberty.h (dupargv): Change arg to char * const *.
 812         (writeargv, countargv): Likewise.
 813
 814 2016-01-01  Alan Modra  <amodra@gmail.com>
 815
 816         Update year range in copyright notice of all files.
 817
 818 For older changes see ChangeLog-0415, aout/ChangeLog-9115,
 819 cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
 820 mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
 821 som/ChangeLog-1015, and vms/ChangeLog-1015
 822 \f
 823 Copyright (C) 2016 Free Software Foundation, Inc.
 824
 825 Copying and distribution of this file, with or without modification,
 826 are permitted in any medium without royalty provided the copyright
 827 notice and this notice are preserved.
 828
 829 Local Variables:
 830 mode: change-log
 831 left-margin: 8
 832 fill-column: 74
 833 version-control: never
 834 End: