include/ChangeLog

   1 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * opcode/mips.h: Replace `0' and `4' operand codes with `.' and
   4         `F' respectively.
   5
   6 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
   7
   8         * opcode/mips.h (INSN2_SHORT_ONLY): New macro.
   9
  10 2016-12-21  Alan Modra  <amodra@gmail.com>
  11
  12         * coff/pe.h: Fix comment chars with high bit set.
  13         * opcode/xgate.h: Likewise.
  14
  15 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  16
  17         * opcode/mips.h (mips_opcode_32bit_p): New inline function.
  18
  19 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  20
  21         * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
  22         (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
  23         (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
  24         (EF_RISCV_FLOAT_ABI_QUAD): Define.
  25
  26 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  27             Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  28
  29         * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
  30
  31 2016-12-16  fincs  <fincs.alt1@gmail.com>
  32
  33         * bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
  34
  35 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  36
  37         * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
  38         typedef as `elf_internal_abiflags_v0'.
  39
  40 2016-12-13 Renlin Li <renlin.li@arm.com>
  41
  42         * opcode/aarch64.h (aarch64_operand_class): Remove
  43         AARCH64_OPND_CLASS_CP_REG.
  44         (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
  45         AARCH64_OPND_Cm to AARCH64_OPND_CRm.
  46         (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
  47
  48 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  49
  50         * opcode/mips.h: Remove references to `>' operand code.
  51
  52 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  53
  54         * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
  55
  56 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  57
  58         * opcode/mips.h (ASE_DSPR3): Add a comment.
  59
  60 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  61
  62         * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
  63         (ARM_ARCH_V8_3A): New.
  64
  65 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  66
  67         * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
  68         instruction classes.
  69
  70 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  71
  72         * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
  73         hwcaps2.
  74
  75 2016-11-22  Alan Modra  <amodra@gmail.com>
  76
  77         PR 20744
  78         * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
  79
  80 2016-11-03  David Tolnay <dtolnay@gmail.com>
  81             Mark Wielaard  <mark@klomp.org>
  82
  83         * demangle.h (DMGL_RUST): New macro.
  84         (DMGL_STYLE_MASK): Add DMGL_RUST.
  85         (demangling_styles): Add dlang_rust.
  86         (RUST_DEMANGLING_STYLE_STRING): New macro.
  87         (RUST_DEMANGLING): New macro.
  88         (rust_demangle): New prototype.
  89         (rust_is_mangled): Likewise.
  90         (rust_demangle_sym): Likewise.
  91
  92 2016-11-07  Jason Merrill  <jason@redhat.com>
  93
  94         * demangle.h (enum demangle_component_type): Add
  95         DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
  96
  97 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  98
  99         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
 100         AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
 101         (enum aarch64_op): Add OP_FCMLA_ELEM.
 102
 103 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 104
 105         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
 106         (enum aarch64_insn_class): Add ldst_imm10.
 107
 108 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 109
 110         * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
 111
 112 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 113
 114         * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
 115         (AARCH64_ARCH_V8_3): Define.
 116         (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
 117
 118 2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 119
 120         * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
 121         (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
 122         (ARM_ARCH_V8M_MAIN_DSP): Likewise.
 123
 124 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 125
 126         * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
 127
 128 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 129
 130         * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
 131         fields.
 132         (struct arc_long_opcode): Delete.
 133         (struct arc_operand): Change types for insert and extract
 134         handlers.
 135
 136 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 137
 138         * opcode/arc.h: Make macros 64-bit safe.
 139
 140 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 141
 142         * opcode/arc.h (arc_opcode_len): Declare.
 143         (ARC_SHORT): Delete.
 144
 145 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 146             Andrew Waterman <andrew@sifive.com>
 147
 148         Add support for RISC-V architecture.
 149         * dis-asm.h: Add prototypes for print_insn_riscv and
 150         print_riscv_disassembler_options.
 151         * elf/riscv.h: New file.
 152         * opcode/riscv-opc.h: New file.
 153         * opcode/riscv.h: New file.
 154
 155 2016-10-17  Nick Clifton  <nickc@redhat.com>
 156
 157         * elf/common.h (DT_SYMTAB_SHNDX): Define.
 158         (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
 159         (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
 160         (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
 161         (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
 162         (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
 163         (ELFOSABI_OPENVOS): Define.
 164         (GRP_MASKOS, GRP_MASKPROC): Define.
 165
 166 2016-10-14  Pedro Alves  <palves@redhat.com>
 167
 168         * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
 169         OVERRIDE): Define as empty.
 170         [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
 171         __final.
 172         [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
 173         empty.
 174
 175 2016-10-14  Pedro Alves  <palves@redhat.com>
 176
 177         * ansidecl.h (GCC_FINAL): Delete.
 178         (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
 179
 180 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 181
 182         * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
 183
 184 2016-09-29  Alan Modra  <amodra@gmail.com>
 185
 186         * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
 187
 188 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 189
 190         * opcode/arc.h (insn_class_t): Add two new classes.
 191
 192 2016-09-26  Alan Modra  <amodra@gmail.com>
 193
 194         * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
 195
 196 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 197
 198         * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
 199
 200 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 201
 202         * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
 203         (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
 204         (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
 205         (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
 206
 207 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 208
 209         * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
 210         (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
 211         (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
 212         aarch64_insn_classes.
 213
 214 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 215
 216         * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
 217         (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
 218         (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
 219
 220 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 221
 222         * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
 223         (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
 224         (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
 225
 226 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 227
 228         * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
 229         (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
 230         (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
 231         (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
 232         (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
 233         (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
 234         (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
 235         (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
 236         (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
 237         (AARCH64_OPND_SVE_UIMM8_53): Likewise.
 238         (aarch64_sve_dupm_mov_immediate_p): Declare.
 239
 240 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 241
 242         * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
 243         (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
 244         (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
 245         (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
 246         (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
 247
 248 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 249
 250         * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
 251         (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
 252         (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
 253         (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
 254         (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
 255         (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
 256         (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
 257         (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
 258         (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
 259         (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
 260         (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
 261         (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
 262         (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
 263         (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
 264         (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
 265         (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
 266         Likewise.
 267
 268 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 269
 270         * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
 271         aarch64_opnd.
 272         (AARCH64_MOD_MUL): New aarch64_modifier_kind.
 273         (aarch64_opnd_info): Make shifter.amount an int64_t and
 274         rearrange the fields.
 275
 276 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 277
 278         * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
 279         (AARCH64_OPND_SVE_PRFOP): Likewise.
 280         (aarch64_sve_pattern_array): Declare.
 281         (aarch64_sve_prfop_array): Likewise.
 282
 283 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 284
 285         * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
 286         (AARCH64_OPND_QLF_P_M): Likewise.
 287
 288 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 289
 290         * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
 291         aarch64_operand_class.
 292         (AARCH64_OPND_CLASS_PRED_REG): Likewise.
 293         (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
 294         (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
 295         (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
 296         (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
 297         (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
 298         (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
 299         (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
 300
 301 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 302
 303         * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
 304         (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
 305
 306 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 307
 308         * opcode/aarch64.h (F_STRICT): New flag.
 309
 310 2016-09-07  Richard Earnshaw  <rearnsha@arm.com>
 311
 312         * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
 313
 314 2016-08-26  Cupertino Miranda  <cmiranda@synopsys.com>
 315         * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
 316         SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
 317         * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
 318         relocation.
 319
 320 2016-08-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 321
 322         * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
 323         (ARM_SET_SYM_CMSE_SPCL): Likewise.
 324
 325 2016-08-01  Andrew Jenner  <andrew@codesourcery.com>
 326
 327         * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
 328
 329 2016-07-29  Aldy Hernandez  <aldyh@redhat.com>
 330
 331         * libiberty.h (MAX_ALLOCA_SIZE): New macro.
 332
 333 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 334
 335         * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
 336         ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
 337         ARC_NUM_ADDRTYPES.
 338         * opcode/arc.h: Add BMU to insn_class_t enum.
 339         * opcode/arc.h: Add PMU to insn_class_t enum.
 340
 341 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 342
 343         * dis-asm.h: Declare print_arc_disassembler_options.
 344
 345 2016-07-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 346
 347         * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
 348         out_implib_bfd fields.
 349
 350 2016-07-14  Claudiu Zissulescu  <claziss@synopsys.com>
 351
 352         * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
 353
 354 2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>
 355
 356         * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
 357         (SHF_ARM_PURECODE): ... this.
 358
 359 2016-07-01  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 360
 361         * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
 362         (AARCH64_CPU_HAS_ANY_FEATURES): New.
 363         (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
 364         (AARCH64_OPCODE_HAS_FEATURE): Remove.
 365
 366 2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>
 367
 368         * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
 369         of enabled FPU features.
 370
 371 2016-06-29  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 372
 373         * opcode/sparc.h (enum sparc_opcode_arch_val): Move
 374         SPARC_OPCODE_ARCH_MAX into the enum.
 375
 376 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 377
 378         * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
 379
 380 2016-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 381
 382         * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
 383
 384 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 385
 386         * elf/xtensa.h (xtensa_make_property_section): New prototype.
 387
 388 2016-06-24  John Baldwin  <jhb@FreeBSD.org>
 389
 390         * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
 391         (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
 392         (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
 393         (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
 394
 395 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 396
 397         * opcode/arc.h: Make insn_class_t alphabetical again.
 398
 399 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 400
 401         * elf/dlx.h: Wrap in extern C.
 402         * elf/xtensa.h: Likewise.
 403         * opcode/arc.h: Likewise.
 404
 405 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 406
 407         * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
 408         tilegx_pipeline.
 409
 410 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 411
 412         * opcode/arc.h: Add nps400 extension and instruction
 413         subclass.
 414         Remove ARC_OPCODE_NPS400
 415         * elf/arc.h: Remove E_ARC_MACH_NPS400
 416
 417 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 418
 419         * opcode/sparc.h (enum sparc_opcode_arch_val): Add
 420         SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
 421         SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
 422         SPARC_OPCODE_ARCH_V9M.
 423
 424 2016-06-14  John Baldwin  <jhb@FreeBSD.org>
 425
 426         * opcode/msp430-decode.h (MSP430_Size): Remove.
 427         (Msp430_Opcode_Decoded): Change type of size to int.
 428
 429 2016-06-11  Alan Modra  <amodra@gmail.com>
 430
 431         * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
 432
 433 2016-06-08  Jose E. Marchesi  <jose.marchesi@oracle.com>
 434
 435         * opcode/sparc.h: Add missing documentation for hyperprivileged
 436         registers in rd (%) and rs1 ($).
 437
 438 2016-06-07  Alan Modra  <amodra@gmail.com>
 439
 440         * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
 441         PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
 442         PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
 443         PPC_APUINFO_VLE: Define.
 444
 445 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 446
 447         * opcode/arm.h (ARM_EXT2_RAS): New.  Also align preceding
 448         entries.
 449         (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
 450
 451 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 452
 453         * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
 454         (struct arc_long_opcode): New structure.
 455         (arc_long_opcodes): Declare.
 456         (arc_num_long_opcodes): Declare.
 457
 458 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 459
 460         * elf/mips.h: Add extern "C".
 461         * elf/sh.h: Likewise.
 462         * opcode/d10v.h: Likewise.
 463         * opcode/d30v.h: Likewise.
 464         * opcode/ia64.h: Likewise.
 465         * opcode/mips.h: Likewise.
 466         * opcode/ppc.h: Likewise.
 467         * opcode/sparc.h: Likewise.
 468         * opcode/tic6x.h: Likewise.
 469         * opcode/v850.h: Likewise.
 470
 471 2016-05-28  Alan Modra  <amodra@gmail.com>
 472
 473         * bfdlink.h (struct bfd_link_callbacks): Update comments.
 474         Return void from multiple_definition, multiple_common,
 475         add_to_set, constructor, warning, undefined_symbol,
 476         reloc_overflow, reloc_dangerous and unattached_reloc.
 477
 478 2016-05-26  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 479
 480         * opcode/metag.h: wrap declarations in extern "C".
 481
 482 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 483
 484         * opcode/arc.h (insn_subclass_t): Add COND.
 485         (flag_class_t): Add F_CLASS_EXTEND.
 486
 487 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 488
 489         * opcode/arc.h (struct arc_opcode): Renamed attribute class to
 490         insn_class.
 491         (struct arc_flag_class): Renamed attribute class to flag_class.
 492
 493 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 494
 495         * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
 496         plain symbol.
 497
 498 2016-04-29  Tom Tromey  <tom@tromey.com>
 499
 500         * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
 501         DW_LANG_Rust_old>: New constants.
 502
 503 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 504
 505         * elf/mips.h (AFL_ASE_DSPR3): New macro.
 506         (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
 507         * opcode/mips.h (ASE_DSPR3): New macro.
 508
 509 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 510             Nick Clifton  <nickc@redhat.com>
 511
 512         * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
 513         enumerator.
 514         (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
 515         (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
 516         (ARM_SYM_BRANCH_TYPE): Replace by ...
 517         (ARM_GET_SYM_BRANCH_TYPE): This and ...
 518         (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
 519         BFD_ASSERT is defined or not.
 520
 521 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 522
 523         * elf/arm.h (Tag_DSP_extension): Define.
 524
 525 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 526
 527         * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
 528
 529 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 530
 531         * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
 532         (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
 533         (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
 534         for the high core bits.
 535
 536 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 537
 538         * opcode/arc.h (ARC_SYNTAX_1OP): Declare
 539         (ARC_SYNTAX_NOP): Likewsie.
 540         (ARC_OP1_MUST_BE_IMM): Update defined value.
 541         (ARC_OP1_IMM_IMPLIED): Likewise.
 542         (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
 543
 544 2016-04-28  Nick Clifton  <nickc@redhat.com>
 545
 546         PR target/19722
 547         * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
 548
 549 2016-04-27  Alan Modra  <amodra@gmail.com>
 550
 551         * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
 552         undef.  Formatting.
 553
 554 2016-04-21  Nick Clifton  <nickc@redhat.com>
 555
 556         * bfdlink.h: Add prototype for bfd_link_check_relocs.
 557
 558 2016-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 559
 560         * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
 561
 562 2016-04-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 563
 564         * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
 565
 566 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 567
 568         * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
 569
 570 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 571
 572         * opcode/arc.h (insn_class_t): Add NET and ACL class.
 573
 574 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 575
 576         * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
 577         * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
 578
 579 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 580
 581         * opcode/arc.h (flag_class_t): Update.
 582         (ARC_OPCODE_NONE): Define.
 583         (ARC_OPCODE_ARCALL): Likewise.
 584         (ARC_OPCODE_ARCFPX): Likewise.
 585         (ARC_REGISTER_READONLY): Likewise.
 586         (ARC_REGISTER_WRITEONLY): Likewise.
 587         (ARC_REGISTER_NOSHORT_CUT): Likewise.
 588         (arc_aux_reg): Add cpu.
 589
 590 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 591
 592         * opcode/arc.h (arc_num_opcodes): Remove.
 593         (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
 594         (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
 595         (ARC_SUFFIX_FLAG): Define.
 596         (flags_none, flags_f, flags_cc, flags_ccf): Declare.
 597         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 598         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 599         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 600         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 601         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 602         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 603         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 604         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 605         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 606
 607 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 608
 609         * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
 610         (ARC_FPUDA): Define.
 611         (arc_aux_reg): Add new field.
 612
 613 2016-04-05  Cupertino Miranda  <cmiranda@synopsys.com>
 614
 615         * opcode/arc-func.h (replace_bits24): Changed.
 616         (replace_bits24_be): Created.
 617
 618 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 619
 620         * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
 621         (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
 622         (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
 623         (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
 624         (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
 625         (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
 626         (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
 627         (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
 628         (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
 629         (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
 630         (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
 631         (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
 632         (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
 633         (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
 634
 635 2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 636
 637         * opcode/i960.h: Add const qualifiers.
 638         * opcode/tic4x.h (struct tic4x_inst): Likewise.
 639
 640 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 641
 642         * opcodes/arc.h (insn_class_t): Add BITOP type.
 643
 644 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 645
 646         * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
 647         new classes instead.
 648
 649 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 650
 651         * elf/arc.h (E_ARC_MACH_NPS400): Define.
 652         * opcode/arc.h (ARC_OPCODE_NPS400): Define.
 653
 654 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 655
 656         * elf/arc.h (EF_ARC_CPU_GENERIC): Delete.  Update related comment.
 657
 658 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 659
 660         * elf/arc.h (EF_ARC_MACH): Delete.
 661         (EF_ARC_MACH_MSK): Remove out of date comment.
 662
 663 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 664
 665         * opcode/arc.h (ARC_OPCODE_BASE): Delete.
 666
 667 2016-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 668
 669         PR ld/19807
 670         * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
 671
 672 2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
 673             Andrew Burgess  <andrew.burgess@embecosm.com>
 674
 675         * elf/arc-reloc.def: Add a call to ME within the formula for each
 676         relocation that requires middle-endian correction.
 677
 678 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 679
 680         * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
 681         * opcode/h8300.h (struct h8_opcode): Likewise.
 682         * opcode/hppa.h (struct pa_opcode): Likewise.
 683         * opcode/msp430.h: Likewise.
 684         * opcode/spu.h (struct spu_opcode): Likewise.
 685         * opcode/tic30.h (struct _register): Likewise.
 686         * opcode/tic4x.h (struct tic4x_register): Likewise.
 687         (struct tic4x_cond): Likewise.
 688         (struct tic4x_indirect): Likewise.
 689         (struct tic4x_inst): Likewise.
 690         * opcode/visium.h (struct reg_entry): Likewise.
 691
 692 2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>
 693
 694         * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
 695         (ARM_CPU_HAS_FEATURE): Add comment.
 696
 697 2016-03-03  Than McIntosh <thanm@google.com>
 698
 699         * plugin-api.h: Add new hooks to the plugin transfer vector to
 700         to support querying section alignment and section size.
 701         (ld_plugin_get_input_section_alignment): New hook.
 702         (ld_plugin_get_input_section_size): New hook.
 703         (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
 704         and LDPT_GET_INPUT_SECTION_SIZE.
 705         (ld_plugin_tv): Add tv_get_input_section_alignment and
 706         tv_get_input_section_size.
 707
 708 2016-03-03  Evgenii Stepanov  <eugenis@google.com>
 709
 710         * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
 711
 712 2016-02-26  H.J. Lu  <hongjiu.lu@intel.com>
 713
 714         PR ld/19645
 715         * bfdlink.h (bfd_link_elf_stt_common): New enum.
 716         (bfd_link_info): Add elf_stt_common.
 717
 718 2016-02-26  H.J. Lu  <hongjiu.lu@intel.com>
 719
 720         PR ld/19636
 721         PR ld/19704
 722         PR ld/19719
 723         * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
 724
 725 2016-02-19  Matthew Wahab  <matthew.wahab@arm.com>
 726             Jiong Wang  <jiong.wang@arm.com>
 727
 728         * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
 729
 730 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 731             Janek van Oirschot  <jvanoirs@synopsys.com>
 732
 733         * opcode/arc.h (arc_opcode arc_relax_opcodes)
 734         (arc_num_relax_opcodes): Declare.
 735
 736 2016-02-09  Nick Clifton  <nickc@redhat.com>
 737
 738         * opcode/metag.h (metag_scondtab): Mark as possibly unused.
 739         * opcode/nds32.h (nds32_r45map): Likewise.
 740         (nds32_r54map): Likewise.
 741         * opcode/visium.h (gen_reg_table): Likewise.
 742         (fp_reg_table, cc_table, opcode_table): Likewise.
 743
 744 2016-02-09  Alan Modra  <amodra@gmail.com>
 745
 746         PR 16583
 747         * elf/common.h (AT_SUN_HWCAP): Undef before defining.
 748
 749 2016-02-04  Nick Clifton  <nickc@redhat.com>
 750
 751         PR target/19561
 752         * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
 753         (RRUX): Synthesise using case 2 rather than 7.
 754
 755 2016-01-19  John Baldwin  <jhb@FreeBSD.org>
 756
 757         * elf/common.h (NT_FREEBSD_THRMISC): Define.
 758         (NT_FREEBSD_PROCSTAT_PROC): Define.
 759         (NT_FREEBSD_PROCSTAT_FILES): Define.
 760         (NT_FREEBSD_PROCSTAT_VMMAP): Define.
 761         (NT_FREEBSD_PROCSTAT_GROUPS): Define.
 762         (NT_FREEBSD_PROCSTAT_UMASK): Define.
 763         (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
 764         (NT_FREEBSD_PROCSTAT_OSREL): Define.
 765         (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
 766         (NT_FREEBSD_PROCSTAT_AUXV): Define.
 767
 768 2016-01-18  Miranda Cupertino  <Cupertino.Miranda@synopsys.com>
 769             Zissulescu Claudiu  <Claudiu.Zissulescu@synopsys.com>
 770
 771         * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
 772         (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
 773         (ARC_TLS_LE_32): Fixed formula.
 774         (ARC_TLS_GD_LD): Use new special function.
 775         * opcode/arc-func.h: Changed all the replacement
 776         functions to clear the patching bits before doing an or it with the value
 777         argument.
 778
 779 2016-01-18  Nick Clifton  <nickc@redhat.com>
 780
 781         PR ld/19440
 782         * coff/internal.h (internal_syment): Use int to hold section
 783         number.
 784         (N_UNDEF): Cast to int not short.
 785         (N_ABS): Likewise.
 786         (N_DEBUG): Likewise.
 787         (N_TV): Likewise.
 788         (P_TV): Likewise.
 789
 790 2016-01-11  Nick Clifton  <nickc@redhat.com>
 791
 792         Import this change from GCC mainline:
 793
 794         2016-01-07  Mike Frysinger  <vapier@gentoo.org>
 795
 796         * longlong.h: Change !__SHMEDIA__ to
 797         (!defined (__SHMEDIA__) || !__SHMEDIA__).
 798         Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
 799
 800 2016-01-06  Maciej W. Rozycki  <macro@imgtec.com>
 801
 802         * opcode/mips.h: Add a summary of MIPS16 operand codes.
 803
 804 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 805
 806         * libiberty.h (dupargv): Change arg to char * const *.
 807         (writeargv, countargv): Likewise.
 808
 809 2016-01-01  Alan Modra  <amodra@gmail.com>
 810
 811         Update year range in copyright notice of all files.
 812
 813 For older changes see ChangeLog-0415, aout/ChangeLog-9115,
 814 cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
 815 mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
 816 som/ChangeLog-1015, and vms/ChangeLog-1015
 817 \f
 818 Copyright (C) 2016 Free Software Foundation, Inc.
 819
 820 Copying and distribution of this file, with or without modification,
 821 are permitted in any medium without royalty provided the copyright
 822 notice and this notice are preserved.
 823
 824 Local Variables:
 825 mode: change-log
 826 left-margin: 8
 827 fill-column: 74
 828 version-control: never
 829 End: