include/drm-uapi/amdgpu_drm.h

   1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * Copyright 2014 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32 #ifndef __AMDGPU_DRM_H__
  33 #define __AMDGPU_DRM_H__
  34
  35 #include "drm.h"
  36
  37 #if defined(__cplusplus)
  38 extern "C" {
  39 #endif
  40
  41 #define DRM_AMDGPU_GEM_CREATE           0x00
  42 #define DRM_AMDGPU_GEM_MMAP             0x01
  43 #define DRM_AMDGPU_CTX                  0x02
  44 #define DRM_AMDGPU_BO_LIST              0x03
  45 #define DRM_AMDGPU_CS                   0x04
  46 #define DRM_AMDGPU_INFO                 0x05
  47 #define DRM_AMDGPU_GEM_METADATA         0x06
  48 #define DRM_AMDGPU_GEM_WAIT_IDLE        0x07
  49 #define DRM_AMDGPU_GEM_VA               0x08
  50 #define DRM_AMDGPU_WAIT_CS              0x09
  51 #define DRM_AMDGPU_GEM_OP               0x10
  52 #define DRM_AMDGPU_GEM_USERPTR          0x11
  53 #define DRM_AMDGPU_WAIT_FENCES          0x12
  54 #define DRM_AMDGPU_VM                   0x13
  55 #define DRM_AMDGPU_FENCE_TO_HANDLE      0x14
  56 #define DRM_AMDGPU_SCHED                0x15
  57
  58 #define DRM_IOCTL_AMDGPU_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
  59 #define DRM_IOCTL_AMDGPU_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
  60 #define DRM_IOCTL_AMDGPU_CTX            DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
  61 #define DRM_IOCTL_AMDGPU_BO_LIST        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
  62 #define DRM_IOCTL_AMDGPU_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
  63 #define DRM_IOCTL_AMDGPU_INFO           DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
  64 #define DRM_IOCTL_AMDGPU_GEM_METADATA   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
  65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
  66 #define DRM_IOCTL_AMDGPU_GEM_VA         DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
  67 #define DRM_IOCTL_AMDGPU_WAIT_CS        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
  68 #define DRM_IOCTL_AMDGPU_GEM_OP         DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
  69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
  70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
  71 #define DRM_IOCTL_AMDGPU_VM             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
  72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
  73 #define DRM_IOCTL_AMDGPU_SCHED          DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
  74
  75 /**
  76  * DOC: memory domains
  77  *
  78  * %AMDGPU_GEM_DOMAIN_CPU       System memory that is not GPU accessible.
  79  * Memory in this pool could be swapped out to disk if there is pressure.
  80  *
  81  * %AMDGPU_GEM_DOMAIN_GTT       GPU accessible system memory, mapped into the
  82  * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
  83  * pages of system memory, allows GPU access system memory in a linezrized
  84  * fashion.
  85  *
  86  * %AMDGPU_GEM_DOMAIN_VRAM      Local video memory. For APUs, it is memory
  87  * carved out by the BIOS.
  88  *
  89  * %AMDGPU_GEM_DOMAIN_GDS       Global on-chip data storage used to share data
  90  * across shader threads.
  91  *
  92  * %AMDGPU_GEM_DOMAIN_GWS       Global wave sync, used to synchronize the
  93  * execution of all the waves on a device.
  94  *
  95  * %AMDGPU_GEM_DOMAIN_OA        Ordered append, used by 3D or Compute engines
  96  * for appending data.
  97  */
  98 #define AMDGPU_GEM_DOMAIN_CPU           0x1
  99 #define AMDGPU_GEM_DOMAIN_GTT           0x2
 100 #define AMDGPU_GEM_DOMAIN_VRAM          0x4
 101 #define AMDGPU_GEM_DOMAIN_GDS           0x8
 102 #define AMDGPU_GEM_DOMAIN_GWS           0x10
 103 #define AMDGPU_GEM_DOMAIN_OA            0x20
 104 #define AMDGPU_GEM_DOMAIN_MASK          (AMDGPU_GEM_DOMAIN_CPU | \
 105                                          AMDGPU_GEM_DOMAIN_GTT | \
 106                                          AMDGPU_GEM_DOMAIN_VRAM | \
 107                                          AMDGPU_GEM_DOMAIN_GDS | \
 108                                          AMDGPU_GEM_DOMAIN_GWS | \
 109                                          AMDGPU_GEM_DOMAIN_OA)
 110
 111 /* Flag that CPU access will be required for the case of VRAM domain */
 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED   (1 << 0)
 113 /* Flag that CPU access will not work, this VRAM domain is invisible */
 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS         (1 << 1)
 115 /* Flag that USWC attributes should be used for GTT */
 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC          (1 << 2)
 117 /* Flag that the memory should be in VRAM and cleared */
 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED          (1 << 3)
 119 /* Flag that create shadow bo(GTT) while allocating vram bo */
 120 #define AMDGPU_GEM_CREATE_SHADOW                (1 << 4)
 121 /* Flag that allocating the BO should use linear VRAM */
 122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS       (1 << 5)
 123 /* Flag that BO is always valid in this VM */
 124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID       (1 << 6)
 125 /* Flag that BO sharing will be explicitly synchronized */
 126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC         (1 << 7)
 127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
 128  * for the second page onward should be set to NC. It should never
 129  * be used by user space applications.
 130  */
 131 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9           (1 << 8)
 132 /* Flag that BO may contain sensitive data that must be wiped before
 133  * releasing the memory
 134  */
 135 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE  (1 << 9)
 136 /* Flag that BO will be encrypted and that the TMZ bit should be
 137  * set in the PTEs when mapping this buffer via GPUVM or
 138  * accessing it with various hw blocks
 139  */
 140 #define AMDGPU_GEM_CREATE_ENCRYPTED             (1 << 10)
 141
 142 struct drm_amdgpu_gem_create_in  {
 143         /** the requested memory size */
 144         __u64 bo_size;
 145         /** physical start_addr alignment in bytes for some HW requirements */
 146         __u64 alignment;
 147         /** the requested memory domains */
 148         __u64 domains;
 149         /** allocation flags */
 150         __u64 domain_flags;
 151 };
 152
 153 struct drm_amdgpu_gem_create_out  {
 154         /** returned GEM object handle */
 155         __u32 handle;
 156         __u32 _pad;
 157 };
 158
 159 union drm_amdgpu_gem_create {
 160         struct drm_amdgpu_gem_create_in         in;
 161         struct drm_amdgpu_gem_create_out        out;
 162 };
 163
 164 /** Opcode to create new residency list.  */
 165 #define AMDGPU_BO_LIST_OP_CREATE        0
 166 /** Opcode to destroy previously created residency list */
 167 #define AMDGPU_BO_LIST_OP_DESTROY       1
 168 /** Opcode to update resource information in the list */
 169 #define AMDGPU_BO_LIST_OP_UPDATE        2
 170
 171 struct drm_amdgpu_bo_list_in {
 172         /** Type of operation */
 173         __u32 operation;
 174         /** Handle of list or 0 if we want to create one */
 175         __u32 list_handle;
 176         /** Number of BOs in list  */
 177         __u32 bo_number;
 178         /** Size of each element describing BO */
 179         __u32 bo_info_size;
 180         /** Pointer to array describing BOs */
 181         __u64 bo_info_ptr;
 182 };
 183
 184 struct drm_amdgpu_bo_list_entry {
 185         /** Handle of BO */
 186         __u32 bo_handle;
 187         /** New (if specified) BO priority to be used during migration */
 188         __u32 bo_priority;
 189 };
 190
 191 struct drm_amdgpu_bo_list_out {
 192         /** Handle of resource list  */
 193         __u32 list_handle;
 194         __u32 _pad;
 195 };
 196
 197 union drm_amdgpu_bo_list {
 198         struct drm_amdgpu_bo_list_in in;
 199         struct drm_amdgpu_bo_list_out out;
 200 };
 201
 202 /* context related */
 203 #define AMDGPU_CTX_OP_ALLOC_CTX 1
 204 #define AMDGPU_CTX_OP_FREE_CTX  2
 205 #define AMDGPU_CTX_OP_QUERY_STATE       3
 206 #define AMDGPU_CTX_OP_QUERY_STATE2      4
 207
 208 /* GPU reset status */
 209 #define AMDGPU_CTX_NO_RESET             0
 210 /* this the context caused it */
 211 #define AMDGPU_CTX_GUILTY_RESET         1
 212 /* some other context caused it */
 213 #define AMDGPU_CTX_INNOCENT_RESET       2
 214 /* unknown cause */
 215 #define AMDGPU_CTX_UNKNOWN_RESET        3
 216
 217 /* indicate gpu reset occured after ctx created */
 218 #define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
 219 /* indicate vram lost occured after ctx created */
 220 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
 221 /* indicate some job from this context once cause gpu hang */
 222 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
 223 /* indicate some errors are detected by RAS */
 224 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE   (1<<3)
 225 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE   (1<<4)
 226
 227 /* Context priority level */
 228 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
 229 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
 230 #define AMDGPU_CTX_PRIORITY_LOW         -512
 231 #define AMDGPU_CTX_PRIORITY_NORMAL      0
 232 /*
 233  * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
 234  * CAP_SYS_NICE or DRM_MASTER
 235 */
 236 #define AMDGPU_CTX_PRIORITY_HIGH        512
 237 #define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
 238
 239 struct drm_amdgpu_ctx_in {
 240         /** AMDGPU_CTX_OP_* */
 241         __u32   op;
 242         /** For future use, no flags defined so far */
 243         __u32   flags;
 244         __u32   ctx_id;
 245         /** AMDGPU_CTX_PRIORITY_* */
 246         __s32   priority;
 247 };
 248
 249 union drm_amdgpu_ctx_out {
 250                 struct {
 251                         __u32   ctx_id;
 252                         __u32   _pad;
 253                 } alloc;
 254
 255                 struct {
 256                         /** For future use, no flags defined so far */
 257                         __u64   flags;
 258                         /** Number of resets caused by this context so far. */
 259                         __u32   hangs;
 260                         /** Reset status since the last call of the ioctl. */
 261                         __u32   reset_status;
 262                 } state;
 263 };
 264
 265 union drm_amdgpu_ctx {
 266         struct drm_amdgpu_ctx_in in;
 267         union drm_amdgpu_ctx_out out;
 268 };
 269
 270 /* vm ioctl */
 271 #define AMDGPU_VM_OP_RESERVE_VMID       1
 272 #define AMDGPU_VM_OP_UNRESERVE_VMID     2
 273
 274 struct drm_amdgpu_vm_in {
 275         /** AMDGPU_VM_OP_* */
 276         __u32   op;
 277         __u32   flags;
 278 };
 279
 280 struct drm_amdgpu_vm_out {
 281         /** For future use, no flags defined so far */
 282         __u64   flags;
 283 };
 284
 285 union drm_amdgpu_vm {
 286         struct drm_amdgpu_vm_in in;
 287         struct drm_amdgpu_vm_out out;
 288 };
 289
 290 /* sched ioctl */
 291 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE       1
 292 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE       2
 293
 294 struct drm_amdgpu_sched_in {
 295         /* AMDGPU_SCHED_OP_* */
 296         __u32   op;
 297         __u32   fd;
 298         /** AMDGPU_CTX_PRIORITY_* */
 299         __s32   priority;
 300         __u32   ctx_id;
 301 };
 302
 303 union drm_amdgpu_sched {
 304         struct drm_amdgpu_sched_in in;
 305 };
 306
 307 /*
 308  * This is not a reliable API and you should expect it to fail for any
 309  * number of reasons and have fallback path that do not use userptr to
 310  * perform any operation.
 311  */
 312 #define AMDGPU_GEM_USERPTR_READONLY     (1 << 0)
 313 #define AMDGPU_GEM_USERPTR_ANONONLY     (1 << 1)
 314 #define AMDGPU_GEM_USERPTR_VALIDATE     (1 << 2)
 315 #define AMDGPU_GEM_USERPTR_REGISTER     (1 << 3)
 316
 317 struct drm_amdgpu_gem_userptr {
 318         __u64           addr;
 319         __u64           size;
 320         /* AMDGPU_GEM_USERPTR_* */
 321         __u32           flags;
 322         /* Resulting GEM handle */
 323         __u32           handle;
 324 };
 325
 326 /* SI-CI-VI: */
 327 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
 328 #define AMDGPU_TILING_ARRAY_MODE_SHIFT                  0
 329 #define AMDGPU_TILING_ARRAY_MODE_MASK                   0xf
 330 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT                 4
 331 #define AMDGPU_TILING_PIPE_CONFIG_MASK                  0x1f
 332 #define AMDGPU_TILING_TILE_SPLIT_SHIFT                  9
 333 #define AMDGPU_TILING_TILE_SPLIT_MASK                   0x7
 334 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT             12
 335 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK              0x7
 336 #define AMDGPU_TILING_BANK_WIDTH_SHIFT                  15
 337 #define AMDGPU_TILING_BANK_WIDTH_MASK                   0x3
 338 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT                 17
 339 #define AMDGPU_TILING_BANK_HEIGHT_MASK                  0x3
 340 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT           19
 341 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK            0x3
 342 #define AMDGPU_TILING_NUM_BANKS_SHIFT                   21
 343 #define AMDGPU_TILING_NUM_BANKS_MASK                    0x3
 344
 345 /* GFX9 and later: */
 346 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT                0
 347 #define AMDGPU_TILING_SWIZZLE_MODE_MASK                 0x1f
 348 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT             5
 349 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK              0xFFFFFF
 350 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT               29
 351 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK                0x3FFF
 352 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT         43
 353 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK          0x1
 354 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT        44
 355 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK         0x1
 356 #define AMDGPU_TILING_SCANOUT_SHIFT                     63
 357 #define AMDGPU_TILING_SCANOUT_MASK                      0x1
 358
 359 /* Set/Get helpers for tiling flags. */
 360 #define AMDGPU_TILING_SET(field, value) \
 361         (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 362 #define AMDGPU_TILING_GET(value, field) \
 363         (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 364
 365 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 366 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 367
 368 /** The same structure is shared for input/output */
 369 struct drm_amdgpu_gem_metadata {
 370         /** GEM Object handle */
 371         __u32   handle;
 372         /** Do we want get or set metadata */
 373         __u32   op;
 374         struct {
 375                 /** For future use, no flags defined so far */
 376                 __u64   flags;
 377                 /** family specific tiling info */
 378                 __u64   tiling_info;
 379                 __u32   data_size_bytes;
 380                 __u32   data[64];
 381         } data;
 382 };
 383
 384 struct drm_amdgpu_gem_mmap_in {
 385         /** the GEM object handle */
 386         __u32 handle;
 387         __u32 _pad;
 388 };
 389
 390 struct drm_amdgpu_gem_mmap_out {
 391         /** mmap offset from the vma offset manager */
 392         __u64 addr_ptr;
 393 };
 394
 395 union drm_amdgpu_gem_mmap {
 396         struct drm_amdgpu_gem_mmap_in   in;
 397         struct drm_amdgpu_gem_mmap_out out;
 398 };
 399
 400 struct drm_amdgpu_gem_wait_idle_in {
 401         /** GEM object handle */
 402         __u32 handle;
 403         /** For future use, no flags defined so far */
 404         __u32 flags;
 405         /** Absolute timeout to wait */
 406         __u64 timeout;
 407 };
 408
 409 struct drm_amdgpu_gem_wait_idle_out {
 410         /** BO status:  0 - BO is idle, 1 - BO is busy */
 411         __u32 status;
 412         /** Returned current memory domain */
 413         __u32 domain;
 414 };
 415
 416 union drm_amdgpu_gem_wait_idle {
 417         struct drm_amdgpu_gem_wait_idle_in  in;
 418         struct drm_amdgpu_gem_wait_idle_out out;
 419 };
 420
 421 struct drm_amdgpu_wait_cs_in {
 422         /* Command submission handle
 423          * handle equals 0 means none to wait for
 424          * handle equals ~0ull means wait for the latest sequence number
 425          */
 426         __u64 handle;
 427         /** Absolute timeout to wait */
 428         __u64 timeout;
 429         __u32 ip_type;
 430         __u32 ip_instance;
 431         __u32 ring;
 432         __u32 ctx_id;
 433 };
 434
 435 struct drm_amdgpu_wait_cs_out {
 436         /** CS status:  0 - CS completed, 1 - CS still busy */
 437         __u64 status;
 438 };
 439
 440 union drm_amdgpu_wait_cs {
 441         struct drm_amdgpu_wait_cs_in in;
 442         struct drm_amdgpu_wait_cs_out out;
 443 };
 444
 445 struct drm_amdgpu_fence {
 446         __u32 ctx_id;
 447         __u32 ip_type;
 448         __u32 ip_instance;
 449         __u32 ring;
 450         __u64 seq_no;
 451 };
 452
 453 struct drm_amdgpu_wait_fences_in {
 454         /** This points to uint64_t * which points to fences */
 455         __u64 fences;
 456         __u32 fence_count;
 457         __u32 wait_all;
 458         __u64 timeout_ns;
 459 };
 460
 461 struct drm_amdgpu_wait_fences_out {
 462         __u32 status;
 463         __u32 first_signaled;
 464 };
 465
 466 union drm_amdgpu_wait_fences {
 467         struct drm_amdgpu_wait_fences_in in;
 468         struct drm_amdgpu_wait_fences_out out;
 469 };
 470
 471 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO       0
 472 #define AMDGPU_GEM_OP_SET_PLACEMENT             1
 473
 474 /* Sets or returns a value associated with a buffer. */
 475 struct drm_amdgpu_gem_op {
 476         /** GEM object handle */
 477         __u32   handle;
 478         /** AMDGPU_GEM_OP_* */
 479         __u32   op;
 480         /** Input or return value */
 481         __u64   value;
 482 };
 483
 484 #define AMDGPU_VA_OP_MAP                        1
 485 #define AMDGPU_VA_OP_UNMAP                      2
 486 #define AMDGPU_VA_OP_CLEAR                      3
 487 #define AMDGPU_VA_OP_REPLACE                    4
 488
 489 /* Delay the page table update till the next CS */
 490 #define AMDGPU_VM_DELAY_UPDATE          (1 << 0)
 491
 492 /* Mapping flags */
 493 /* readable mapping */
 494 #define AMDGPU_VM_PAGE_READABLE         (1 << 1)
 495 /* writable mapping */
 496 #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
 497 /* executable mapping, new for VI */
 498 #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
 499 /* partially resident texture */
 500 #define AMDGPU_VM_PAGE_PRT              (1 << 4)
 501 /* MTYPE flags use bit 5 to 8 */
 502 #define AMDGPU_VM_MTYPE_MASK            (0xf << 5)
 503 /* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
 504 #define AMDGPU_VM_MTYPE_DEFAULT         (0 << 5)
 505 /* Use Non Coherent MTYPE instead of default MTYPE */
 506 #define AMDGPU_VM_MTYPE_NC              (1 << 5)
 507 /* Use Write Combine MTYPE instead of default MTYPE */
 508 #define AMDGPU_VM_MTYPE_WC              (2 << 5)
 509 /* Use Cache Coherent MTYPE instead of default MTYPE */
 510 #define AMDGPU_VM_MTYPE_CC              (3 << 5)
 511 /* Use UnCached MTYPE instead of default MTYPE */
 512 #define AMDGPU_VM_MTYPE_UC              (4 << 5)
 513 /* Use Read Write MTYPE instead of default MTYPE */
 514 #define AMDGPU_VM_MTYPE_RW              (5 << 5)
 515
 516 struct drm_amdgpu_gem_va {
 517         /** GEM object handle */
 518         __u32 handle;
 519         __u32 _pad;
 520         /** AMDGPU_VA_OP_* */
 521         __u32 operation;
 522         /** AMDGPU_VM_PAGE_* */
 523         __u32 flags;
 524         /** va address to assign . Must be correctly aligned.*/
 525         __u64 va_address;
 526         /** Specify offset inside of BO to assign. Must be correctly aligned.*/
 527         __u64 offset_in_bo;
 528         /** Specify mapping size. Must be correctly aligned. */
 529         __u64 map_size;
 530 };
 531
 532 #define AMDGPU_HW_IP_GFX          0
 533 #define AMDGPU_HW_IP_COMPUTE      1
 534 #define AMDGPU_HW_IP_DMA          2
 535 #define AMDGPU_HW_IP_UVD          3
 536 #define AMDGPU_HW_IP_VCE          4
 537 #define AMDGPU_HW_IP_UVD_ENC      5
 538 #define AMDGPU_HW_IP_VCN_DEC      6
 539 #define AMDGPU_HW_IP_VCN_ENC      7
 540 #define AMDGPU_HW_IP_VCN_JPEG     8
 541 #define AMDGPU_HW_IP_NUM          9
 542
 543 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 544
 545 #define AMDGPU_CHUNK_ID_IB              0x01
 546 #define AMDGPU_CHUNK_ID_FENCE           0x02
 547 #define AMDGPU_CHUNK_ID_DEPENDENCIES    0x03
 548 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
 549 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 550 #define AMDGPU_CHUNK_ID_BO_HANDLES      0x06
 551 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES  0x07
 552 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x08
 553 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x09
 554
 555 struct drm_amdgpu_cs_chunk {
 556         __u32           chunk_id;
 557         __u32           length_dw;
 558         __u64           chunk_data;
 559 };
 560
 561 struct drm_amdgpu_cs_in {
 562         /** Rendering context id */
 563         __u32           ctx_id;
 564         /**  Handle of resource list associated with CS */
 565         __u32           bo_list_handle;
 566         __u32           num_chunks;
 567         __u32           flags;
 568         /** this points to __u64 * which point to cs chunks */
 569         __u64           chunks;
 570 };
 571
 572 struct drm_amdgpu_cs_out {
 573         __u64 handle;
 574 };
 575
 576 union drm_amdgpu_cs {
 577         struct drm_amdgpu_cs_in in;
 578         struct drm_amdgpu_cs_out out;
 579 };
 580
 581 /* Specify flags to be used for IB */
 582
 583 /* This IB should be submitted to CE */
 584 #define AMDGPU_IB_FLAG_CE       (1<<0)
 585
 586 /* Preamble flag, which means the IB could be dropped if no context switch */
 587 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 588
 589 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
 590 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
 591
 592 /* The IB fence should do the L2 writeback but not invalidate any shader
 593  * caches (L2/vL1/sL1/I$). */
 594 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
 595
 596 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
 597  * This will reset wave ID counters for the IB.
 598  */
 599 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
 600
 601 /* Flag the IB as secure (TMZ)
 602  */
 603 #define AMDGPU_IB_FLAGS_SECURE  (1 << 5)
 604
 605 /* Tell KMD to flush and invalidate caches
 606  */
 607 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC  (1 << 6)
 608
 609 struct drm_amdgpu_cs_chunk_ib {
 610         __u32 _pad;
 611         /** AMDGPU_IB_FLAG_* */
 612         __u32 flags;
 613         /** Virtual address to begin IB execution */
 614         __u64 va_start;
 615         /** Size of submission */
 616         __u32 ib_bytes;
 617         /** HW IP to submit to */
 618         __u32 ip_type;
 619         /** HW IP index of the same type to submit to  */
 620         __u32 ip_instance;
 621         /** Ring index to submit to */
 622         __u32 ring;
 623 };
 624
 625 struct drm_amdgpu_cs_chunk_dep {
 626         __u32 ip_type;
 627         __u32 ip_instance;
 628         __u32 ring;
 629         __u32 ctx_id;
 630         __u64 handle;
 631 };
 632
 633 struct drm_amdgpu_cs_chunk_fence {
 634         __u32 handle;
 635         __u32 offset;
 636 };
 637
 638 struct drm_amdgpu_cs_chunk_sem {
 639         __u32 handle;
 640 };
 641
 642 struct drm_amdgpu_cs_chunk_syncobj {
 643        __u32 handle;
 644        __u32 flags;
 645        __u64 point;
 646 };
 647
 648 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ      0
 649 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD   1
 650 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
 651
 652 union drm_amdgpu_fence_to_handle {
 653         struct {
 654                 struct drm_amdgpu_fence fence;
 655                 __u32 what;
 656                 __u32 pad;
 657         } in;
 658         struct {
 659                 __u32 handle;
 660         } out;
 661 };
 662
 663 struct drm_amdgpu_cs_chunk_data {
 664         union {
 665                 struct drm_amdgpu_cs_chunk_ib           ib_data;
 666                 struct drm_amdgpu_cs_chunk_fence        fence_data;
 667         };
 668 };
 669
 670 /**
 671  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
 672  *
 673  */
 674 #define AMDGPU_IDS_FLAGS_FUSION         0x1
 675 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 676
 677 /* indicate if acceleration can be working */
 678 #define AMDGPU_INFO_ACCEL_WORKING               0x00
 679 /* get the crtc_id from the mode object id? */
 680 #define AMDGPU_INFO_CRTC_FROM_ID                0x01
 681 /* query hw IP info */
 682 #define AMDGPU_INFO_HW_IP_INFO                  0x02
 683 /* query hw IP instance count for the specified type */
 684 #define AMDGPU_INFO_HW_IP_COUNT                 0x03
 685 /* timestamp for GL_ARB_timer_query */
 686 #define AMDGPU_INFO_TIMESTAMP                   0x05
 687 /* Query the firmware version */
 688 #define AMDGPU_INFO_FW_VERSION                  0x0e
 689         /* Subquery id: Query VCE firmware version */
 690         #define AMDGPU_INFO_FW_VCE              0x1
 691         /* Subquery id: Query UVD firmware version */
 692         #define AMDGPU_INFO_FW_UVD              0x2
 693         /* Subquery id: Query GMC firmware version */
 694         #define AMDGPU_INFO_FW_GMC              0x03
 695         /* Subquery id: Query GFX ME firmware version */
 696         #define AMDGPU_INFO_FW_GFX_ME           0x04
 697         /* Subquery id: Query GFX PFP firmware version */
 698         #define AMDGPU_INFO_FW_GFX_PFP          0x05
 699         /* Subquery id: Query GFX CE firmware version */
 700         #define AMDGPU_INFO_FW_GFX_CE           0x06
 701         /* Subquery id: Query GFX RLC firmware version */
 702         #define AMDGPU_INFO_FW_GFX_RLC          0x07
 703         /* Subquery id: Query GFX MEC firmware version */
 704         #define AMDGPU_INFO_FW_GFX_MEC          0x08
 705         /* Subquery id: Query SMC firmware version */
 706         #define AMDGPU_INFO_FW_SMC              0x0a
 707         /* Subquery id: Query SDMA firmware version */
 708         #define AMDGPU_INFO_FW_SDMA             0x0b
 709         /* Subquery id: Query PSP SOS firmware version */
 710         #define AMDGPU_INFO_FW_SOS              0x0c
 711         /* Subquery id: Query PSP ASD firmware version */
 712         #define AMDGPU_INFO_FW_ASD              0x0d
 713         /* Subquery id: Query VCN firmware version */
 714         #define AMDGPU_INFO_FW_VCN              0x0e
 715         /* Subquery id: Query GFX RLC SRLC firmware version */
 716         #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
 717         /* Subquery id: Query GFX RLC SRLG firmware version */
 718         #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
 719         /* Subquery id: Query GFX RLC SRLS firmware version */
 720         #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
 721         /* Subquery id: Query DMCU firmware version */
 722         #define AMDGPU_INFO_FW_DMCU             0x12
 723         #define AMDGPU_INFO_FW_TA               0x13
 724         /* Subquery id: Query DMCUB firmware version */
 725         #define AMDGPU_INFO_FW_DMCUB            0x14
 726
 727 /* number of bytes moved for TTM migration */
 728 #define AMDGPU_INFO_NUM_BYTES_MOVED             0x0f
 729 /* the used VRAM size */
 730 #define AMDGPU_INFO_VRAM_USAGE                  0x10
 731 /* the used GTT size */
 732 #define AMDGPU_INFO_GTT_USAGE                   0x11
 733 /* Information about GDS, etc. resource configuration */
 734 #define AMDGPU_INFO_GDS_CONFIG                  0x13
 735 /* Query information about VRAM and GTT domains */
 736 #define AMDGPU_INFO_VRAM_GTT                    0x14
 737 /* Query information about register in MMR address space*/
 738 #define AMDGPU_INFO_READ_MMR_REG                0x15
 739 /* Query information about device: rev id, family, etc. */
 740 #define AMDGPU_INFO_DEV_INFO                    0x16
 741 /* visible vram usage */
 742 #define AMDGPU_INFO_VIS_VRAM_USAGE              0x17
 743 /* number of TTM buffer evictions */
 744 #define AMDGPU_INFO_NUM_EVICTIONS               0x18
 745 /* Query memory about VRAM and GTT domains */
 746 #define AMDGPU_INFO_MEMORY                      0x19
 747 /* Query vce clock table */
 748 #define AMDGPU_INFO_VCE_CLOCK_TABLE             0x1A
 749 /* Query vbios related information */
 750 #define AMDGPU_INFO_VBIOS                       0x1B
 751         /* Subquery id: Query vbios size */
 752         #define AMDGPU_INFO_VBIOS_SIZE          0x1
 753         /* Subquery id: Query vbios image */
 754         #define AMDGPU_INFO_VBIOS_IMAGE         0x2
 755 /* Query UVD handles */
 756 #define AMDGPU_INFO_NUM_HANDLES                 0x1C
 757 /* Query sensor related information */
 758 #define AMDGPU_INFO_SENSOR                      0x1D
 759         /* Subquery id: Query GPU shader clock */
 760         #define AMDGPU_INFO_SENSOR_GFX_SCLK             0x1
 761         /* Subquery id: Query GPU memory clock */
 762         #define AMDGPU_INFO_SENSOR_GFX_MCLK             0x2
 763         /* Subquery id: Query GPU temperature */
 764         #define AMDGPU_INFO_SENSOR_GPU_TEMP             0x3
 765         /* Subquery id: Query GPU load */
 766         #define AMDGPU_INFO_SENSOR_GPU_LOAD             0x4
 767         /* Subquery id: Query average GPU power */
 768         #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER        0x5
 769         /* Subquery id: Query northbridge voltage */
 770         #define AMDGPU_INFO_SENSOR_VDDNB                0x6
 771         /* Subquery id: Query graphics voltage */
 772         #define AMDGPU_INFO_SENSOR_VDDGFX               0x7
 773         /* Subquery id: Query GPU stable pstate shader clock */
 774         #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK               0x8
 775         /* Subquery id: Query GPU stable pstate memory clock */
 776         #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK               0x9
 777 /* Number of VRAM page faults on CPU access. */
 778 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
 779 #define AMDGPU_INFO_VRAM_LOST_COUNTER           0x1F
 780 /* query ras mask of enabled features*/
 781 #define AMDGPU_INFO_RAS_ENABLED_FEATURES        0x20
 782
 783 /* RAS MASK: UMC (VRAM) */
 784 #define AMDGPU_INFO_RAS_ENABLED_UMC                     (1 << 0)
 785 /* RAS MASK: SDMA */
 786 #define AMDGPU_INFO_RAS_ENABLED_SDMA                    (1 << 1)
 787 /* RAS MASK: GFX */
 788 #define AMDGPU_INFO_RAS_ENABLED_GFX                     (1 << 2)
 789 /* RAS MASK: MMHUB */
 790 #define AMDGPU_INFO_RAS_ENABLED_MMHUB                   (1 << 3)
 791 /* RAS MASK: ATHUB */
 792 #define AMDGPU_INFO_RAS_ENABLED_ATHUB                   (1 << 4)
 793 /* RAS MASK: PCIE */
 794 #define AMDGPU_INFO_RAS_ENABLED_PCIE                    (1 << 5)
 795 /* RAS MASK: HDP */
 796 #define AMDGPU_INFO_RAS_ENABLED_HDP                     (1 << 6)
 797 /* RAS MASK: XGMI */
 798 #define AMDGPU_INFO_RAS_ENABLED_XGMI                    (1 << 7)
 799 /* RAS MASK: DF */
 800 #define AMDGPU_INFO_RAS_ENABLED_DF                      (1 << 8)
 801 /* RAS MASK: SMN */
 802 #define AMDGPU_INFO_RAS_ENABLED_SMN                     (1 << 9)
 803 /* RAS MASK: SEM */
 804 #define AMDGPU_INFO_RAS_ENABLED_SEM                     (1 << 10)
 805 /* RAS MASK: MP0 */
 806 #define AMDGPU_INFO_RAS_ENABLED_MP0                     (1 << 11)
 807 /* RAS MASK: MP1 */
 808 #define AMDGPU_INFO_RAS_ENABLED_MP1                     (1 << 12)
 809 /* RAS MASK: FUSE */
 810 #define AMDGPU_INFO_RAS_ENABLED_FUSE                    (1 << 13)
 811
 812 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT  0
 813 #define AMDGPU_INFO_MMR_SE_INDEX_MASK   0xff
 814 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT  8
 815 #define AMDGPU_INFO_MMR_SH_INDEX_MASK   0xff
 816
 817 struct drm_amdgpu_query_fw {
 818         /** AMDGPU_INFO_FW_* */
 819         __u32 fw_type;
 820         /**
 821          * Index of the IP if there are more IPs of
 822          * the same type.
 823          */
 824         __u32 ip_instance;
 825         /**
 826          * Index of the engine. Whether this is used depends
 827          * on the firmware type. (e.g. MEC, SDMA)
 828          */
 829         __u32 index;
 830         __u32 _pad;
 831 };
 832
 833 /* Input structure for the INFO ioctl */
 834 struct drm_amdgpu_info {
 835         /* Where the return value will be stored */
 836         __u64 return_pointer;
 837         /* The size of the return value. Just like "size" in "snprintf",
 838          * it limits how many bytes the kernel can write. */
 839         __u32 return_size;
 840         /* The query request id. */
 841         __u32 query;
 842
 843         union {
 844                 struct {
 845                         __u32 id;
 846                         __u32 _pad;
 847                 } mode_crtc;
 848
 849                 struct {
 850                         /** AMDGPU_HW_IP_* */
 851                         __u32 type;
 852                         /**
 853                          * Index of the IP if there are more IPs of the same
 854                          * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
 855                          */
 856                         __u32 ip_instance;
 857                 } query_hw_ip;
 858
 859                 struct {
 860                         __u32 dword_offset;
 861                         /** number of registers to read */
 862                         __u32 count;
 863                         __u32 instance;
 864                         /** For future use, no flags defined so far */
 865                         __u32 flags;
 866                 } read_mmr_reg;
 867
 868                 struct drm_amdgpu_query_fw query_fw;
 869
 870                 struct {
 871                         __u32 type;
 872                         __u32 offset;
 873                 } vbios_info;
 874
 875                 struct {
 876                         __u32 type;
 877                 } sensor_info;
 878         };
 879 };
 880
 881 struct drm_amdgpu_info_gds {
 882         /** GDS GFX partition size */
 883         __u32 gds_gfx_partition_size;
 884         /** GDS compute partition size */
 885         __u32 compute_partition_size;
 886         /** total GDS memory size */
 887         __u32 gds_total_size;
 888         /** GWS size per GFX partition */
 889         __u32 gws_per_gfx_partition;
 890         /** GSW size per compute partition */
 891         __u32 gws_per_compute_partition;
 892         /** OA size per GFX partition */
 893         __u32 oa_per_gfx_partition;
 894         /** OA size per compute partition */
 895         __u32 oa_per_compute_partition;
 896         __u32 _pad;
 897 };
 898
 899 struct drm_amdgpu_info_vram_gtt {
 900         __u64 vram_size;
 901         __u64 vram_cpu_accessible_size;
 902         __u64 gtt_size;
 903 };
 904
 905 struct drm_amdgpu_heap_info {
 906         /** max. physical memory */
 907         __u64 total_heap_size;
 908
 909         /** Theoretical max. available memory in the given heap */
 910         __u64 usable_heap_size;
 911
 912         /**
 913          * Number of bytes allocated in the heap. This includes all processes
 914          * and private allocations in the kernel. It changes when new buffers
 915          * are allocated, freed, and moved. It cannot be larger than
 916          * heap_size.
 917          */
 918         __u64 heap_usage;
 919
 920         /**
 921          * Theoretical possible max. size of buffer which
 922          * could be allocated in the given heap
 923          */
 924         __u64 max_allocation;
 925 };
 926
 927 struct drm_amdgpu_memory_info {
 928         struct drm_amdgpu_heap_info vram;
 929         struct drm_amdgpu_heap_info cpu_accessible_vram;
 930         struct drm_amdgpu_heap_info gtt;
 931 };
 932
 933 struct drm_amdgpu_info_firmware {
 934         __u32 ver;
 935         __u32 feature;
 936 };
 937
 938 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
 939 #define AMDGPU_VRAM_TYPE_GDDR1 1
 940 #define AMDGPU_VRAM_TYPE_DDR2  2
 941 #define AMDGPU_VRAM_TYPE_GDDR3 3
 942 #define AMDGPU_VRAM_TYPE_GDDR4 4
 943 #define AMDGPU_VRAM_TYPE_GDDR5 5
 944 #define AMDGPU_VRAM_TYPE_HBM   6
 945 #define AMDGPU_VRAM_TYPE_DDR3  7
 946 #define AMDGPU_VRAM_TYPE_DDR4  8
 947 #define AMDGPU_VRAM_TYPE_GDDR6 9
 948
 949 struct drm_amdgpu_info_device {
 950         /** PCI Device ID */
 951         __u32 device_id;
 952         /** Internal chip revision: A0, A1, etc.) */
 953         __u32 chip_rev;
 954         __u32 external_rev;
 955         /** Revision id in PCI Config space */
 956         __u32 pci_rev;
 957         __u32 family;
 958         __u32 num_shader_engines;
 959         __u32 num_shader_arrays_per_engine;
 960         /* in KHz */
 961         __u32 gpu_counter_freq;
 962         __u64 max_engine_clock;
 963         __u64 max_memory_clock;
 964         /* cu information */
 965         __u32 cu_active_number;
 966         /* NOTE: cu_ao_mask is INVALID, DON'T use it */
 967         __u32 cu_ao_mask;
 968         __u32 cu_bitmap[4][4];
 969         /** Render backend pipe mask. One render backend is CB+DB. */
 970         __u32 enabled_rb_pipes_mask;
 971         __u32 num_rb_pipes;
 972         __u32 num_hw_gfx_contexts;
 973         __u32 _pad;
 974         __u64 ids_flags;
 975         /** Starting virtual address for UMDs. */
 976         __u64 virtual_address_offset;
 977         /** The maximum virtual address */
 978         __u64 virtual_address_max;
 979         /** Required alignment of virtual addresses. */
 980         __u32 virtual_address_alignment;
 981         /** Page table entry - fragment size */
 982         __u32 pte_fragment_size;
 983         __u32 gart_page_size;
 984         /** constant engine ram size*/
 985         __u32 ce_ram_size;
 986         /** video memory type info*/
 987         __u32 vram_type;
 988         /** video memory bit width*/
 989         __u32 vram_bit_width;
 990         /* vce harvesting instance */
 991         __u32 vce_harvest_config;
 992         /* gfx double offchip LDS buffers */
 993         __u32 gc_double_offchip_lds_buf;
 994         /* NGG Primitive Buffer */
 995         __u64 prim_buf_gpu_addr;
 996         /* NGG Position Buffer */
 997         __u64 pos_buf_gpu_addr;
 998         /* NGG Control Sideband */
 999         __u64 cntl_sb_buf_gpu_addr;
1000         /* NGG Parameter Cache */
1001         __u64 param_buf_gpu_addr;
1002         __u32 prim_buf_size;
1003         __u32 pos_buf_size;
1004         __u32 cntl_sb_buf_size;
1005         __u32 param_buf_size;
1006         /* wavefront size*/
1007         __u32 wave_front_size;
1008         /* shader visible vgprs*/
1009         __u32 num_shader_visible_vgprs;
1010         /* CU per shader array*/
1011         __u32 num_cu_per_sh;
1012         /* number of tcc blocks*/
1013         __u32 num_tcc_blocks;
1014         /* gs vgt table depth*/
1015         __u32 gs_vgt_table_depth;
1016         /* gs primitive buffer depth*/
1017         __u32 gs_prim_buffer_depth;
1018         /* max gs wavefront per vgt*/
1019         __u32 max_gs_waves_per_vgt;
1020         __u32 _pad1;
1021         /* always on cu bitmap */
1022         __u32 cu_ao_bitmap[4][4];
1023         /** Starting high virtual address for UMDs. */
1024         __u64 high_va_offset;
1025         /** The maximum high virtual address */
1026         __u64 high_va_max;
1027         /* gfx10 pa_sc_tile_steering_override */
1028         __u32 pa_sc_tile_steering_override;
1029         /* disabled TCCs */
1030         __u64 tcc_disabled_mask;
1031 };
1032
1033 struct drm_amdgpu_info_hw_ip {
1034         /** Version of h/w IP */
1035         __u32  hw_ip_version_major;
1036         __u32  hw_ip_version_minor;
1037         /** Capabilities */
1038         __u64  capabilities_flags;
1039         /** command buffer address start alignment*/
1040         __u32  ib_start_alignment;
1041         /** command buffer size alignment*/
1042         __u32  ib_size_alignment;
1043         /** Bitmask of available rings. Bit 0 means ring 0, etc. */
1044         __u32  available_rings;
1045         __u32  _pad;
1046 };
1047
1048 struct drm_amdgpu_info_num_handles {
1049         /** Max handles as supported by firmware for UVD */
1050         __u32  uvd_max_handles;
1051         /** Handles currently in use for UVD */
1052         __u32  uvd_used_handles;
1053 };
1054
1055 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES          6
1056
1057 struct drm_amdgpu_info_vce_clock_table_entry {
1058         /** System clock */
1059         __u32 sclk;
1060         /** Memory clock */
1061         __u32 mclk;
1062         /** VCE clock */
1063         __u32 eclk;
1064         __u32 pad;
1065 };
1066
1067 struct drm_amdgpu_info_vce_clock_table {
1068         struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1069         __u32 num_valid_entries;
1070         __u32 pad;
1071 };
1072
1073 /*
1074  * Supported GPU families
1075  */
1076 #define AMDGPU_FAMILY_UNKNOWN                   0
1077 #define AMDGPU_FAMILY_SI                        110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
1078 #define AMDGPU_FAMILY_CI                        120 /* Bonaire, Hawaii */
1079 #define AMDGPU_FAMILY_KV                        125 /* Kaveri, Kabini, Mullins */
1080 #define AMDGPU_FAMILY_VI                        130 /* Iceland, Tonga */
1081 #define AMDGPU_FAMILY_CZ                        135 /* Carrizo, Stoney */
1082 #define AMDGPU_FAMILY_AI                        141 /* Vega10 */
1083 #define AMDGPU_FAMILY_RV                        142 /* Raven */
1084 #define AMDGPU_FAMILY_NV                        143 /* Navi10 */
1085
1086 #if defined(__cplusplus)
1087 }
1088 #endif
1089
1090 #endif