include/drm-uapi/drm.h

   1 /**
   2  * \file drm.h
   3  * Header for the Direct Rendering Manager
   4  *
   5  * \author Rickard E. (Rik) Faith <faith@valinux.com>
   6  *
   7  * \par Acknowledgments:
   8  * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
   9  */
  10
  11 /*
  12  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  13  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  14  * All rights reserved.
  15  *
  16  * Permission is hereby granted, free of charge, to any person obtaining a
  17  * copy of this software and associated documentation files (the "Software"),
  18  * to deal in the Software without restriction, including without limitation
  19  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  20  * and/or sell copies of the Software, and to permit persons to whom the
  21  * Software is furnished to do so, subject to the following conditions:
  22  *
  23  * The above copyright notice and this permission notice (including the next
  24  * paragraph) shall be included in all copies or substantial portions of the
  25  * Software.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  28  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  29  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  30  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  31  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  32  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  33  * OTHER DEALINGS IN THE SOFTWARE.
  34  */
  35
  36 #ifndef _DRM_H_
  37 #define _DRM_H_
  38
  39 #if   defined(__linux__)
  40
  41 #include <linux/types.h>
  42 #include <asm/ioctl.h>
  43 typedef unsigned int drm_handle_t;
  44
  45 #else /* One of the BSDs */
  46
  47 #include <stdint.h>
  48 #include <sys/ioccom.h>
  49 #include <sys/types.h>
  50 typedef int8_t   __s8;
  51 typedef uint8_t  __u8;
  52 typedef int16_t  __s16;
  53 typedef uint16_t __u16;
  54 typedef int32_t  __s32;
  55 typedef uint32_t __u32;
  56 typedef int64_t  __s64;
  57 typedef uint64_t __u64;
  58 typedef size_t   __kernel_size_t;
  59 typedef unsigned long drm_handle_t;
  60
  61 #endif
  62
  63 #if defined(__cplusplus)
  64 extern "C" {
  65 #endif
  66
  67 #define DRM_NAME        "drm"     /**< Name in kernel, /dev, and /proc */
  68 #define DRM_MIN_ORDER   5         /**< At least 2^5 bytes = 32 bytes */
  69 #define DRM_MAX_ORDER   22        /**< Up to 2^22 bytes = 4MB */
  70 #define DRM_RAM_PERCENT 10        /**< How much system ram can we lock? */
  71
  72 #define _DRM_LOCK_HELD  0x80000000U /**< Hardware lock is held */
  73 #define _DRM_LOCK_CONT  0x40000000U /**< Hardware lock is contended */
  74 #define _DRM_LOCK_IS_HELD(lock)    ((lock) & _DRM_LOCK_HELD)
  75 #define _DRM_LOCK_IS_CONT(lock)    ((lock) & _DRM_LOCK_CONT)
  76 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
  77
  78 typedef unsigned int drm_context_t;
  79 typedef unsigned int drm_drawable_t;
  80 typedef unsigned int drm_magic_t;
  81
  82 /**
  83  * Cliprect.
  84  *
  85  * \warning: If you change this structure, make sure you change
  86  * XF86DRIClipRectRec in the server as well
  87  *
  88  * \note KW: Actually it's illegal to change either for
  89  * backwards-compatibility reasons.
  90  */
  91 struct drm_clip_rect {
  92         unsigned short x1;
  93         unsigned short y1;
  94         unsigned short x2;
  95         unsigned short y2;
  96 };
  97
  98 /**
  99  * Drawable information.
 100  */
 101 struct drm_drawable_info {
 102         unsigned int num_rects;
 103         struct drm_clip_rect *rects;
 104 };
 105
 106 /**
 107  * Texture region,
 108  */
 109 struct drm_tex_region {
 110         unsigned char next;
 111         unsigned char prev;
 112         unsigned char in_use;
 113         unsigned char padding;
 114         unsigned int age;
 115 };
 116
 117 /**
 118  * Hardware lock.
 119  *
 120  * The lock structure is a simple cache-line aligned integer.  To avoid
 121  * processor bus contention on a multiprocessor system, there should not be any
 122  * other data stored in the same cache line.
 123  */
 124 struct drm_hw_lock {
 125         __volatile__ unsigned int lock;         /**< lock variable */
 126         char padding[60];                       /**< Pad to cache line */
 127 };
 128
 129 /**
 130  * DRM_IOCTL_VERSION ioctl argument type.
 131  *
 132  * \sa drmGetVersion().
 133  */
 134 struct drm_version {
 135         int version_major;        /**< Major version */
 136         int version_minor;        /**< Minor version */
 137         int version_patchlevel;   /**< Patch level */
 138         __kernel_size_t name_len;         /**< Length of name buffer */
 139         char *name;       /**< Name of driver */
 140         __kernel_size_t date_len;         /**< Length of date buffer */
 141         char *date;       /**< User-space buffer to hold date */
 142         __kernel_size_t desc_len;         /**< Length of desc buffer */
 143         char *desc;       /**< User-space buffer to hold desc */
 144 };
 145
 146 /**
 147  * DRM_IOCTL_GET_UNIQUE ioctl argument type.
 148  *
 149  * \sa drmGetBusid() and drmSetBusId().
 150  */
 151 struct drm_unique {
 152         __kernel_size_t unique_len;       /**< Length of unique */
 153         char *unique;     /**< Unique name for driver instantiation */
 154 };
 155
 156 struct drm_list {
 157         int count;                /**< Length of user-space structures */
 158         struct drm_version *version;
 159 };
 160
 161 struct drm_block {
 162         int unused;
 163 };
 164
 165 /**
 166  * DRM_IOCTL_CONTROL ioctl argument type.
 167  *
 168  * \sa drmCtlInstHandler() and drmCtlUninstHandler().
 169  */
 170 struct drm_control {
 171         enum {
 172                 DRM_ADD_COMMAND,
 173                 DRM_RM_COMMAND,
 174                 DRM_INST_HANDLER,
 175                 DRM_UNINST_HANDLER
 176         } func;
 177         int irq;
 178 };
 179
 180 /**
 181  * Type of memory to map.
 182  */
 183 enum drm_map_type {
 184         _DRM_FRAME_BUFFER = 0,    /**< WC (no caching), no core dump */
 185         _DRM_REGISTERS = 1,       /**< no caching, no core dump */
 186         _DRM_SHM = 2,             /**< shared, cached */
 187         _DRM_AGP = 3,             /**< AGP/GART */
 188         _DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
 189         _DRM_CONSISTENT = 5       /**< Consistent memory for PCI DMA */
 190 };
 191
 192 /**
 193  * Memory mapping flags.
 194  */
 195 enum drm_map_flags {
 196         _DRM_RESTRICTED = 0x01,      /**< Cannot be mapped to user-virtual */
 197         _DRM_READ_ONLY = 0x02,
 198         _DRM_LOCKED = 0x04,          /**< shared, cached, locked */
 199         _DRM_KERNEL = 0x08,          /**< kernel requires access */
 200         _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
 201         _DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
 202         _DRM_REMOVABLE = 0x40,       /**< Removable mapping */
 203         _DRM_DRIVER = 0x80           /**< Managed by driver */
 204 };
 205
 206 struct drm_ctx_priv_map {
 207         unsigned int ctx_id;     /**< Context requesting private mapping */
 208         void *handle;            /**< Handle of map */
 209 };
 210
 211 /**
 212  * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
 213  * argument type.
 214  *
 215  * \sa drmAddMap().
 216  */
 217 struct drm_map {
 218         unsigned long offset;    /**< Requested physical address (0 for SAREA)*/
 219         unsigned long size;      /**< Requested physical size (bytes) */
 220         enum drm_map_type type;  /**< Type of memory to map */
 221         enum drm_map_flags flags;        /**< Flags */
 222         void *handle;            /**< User-space: "Handle" to pass to mmap() */
 223                                  /**< Kernel-space: kernel-virtual address */
 224         int mtrr;                /**< MTRR slot used */
 225         /*   Private data */
 226 };
 227
 228 /**
 229  * DRM_IOCTL_GET_CLIENT ioctl argument type.
 230  */
 231 struct drm_client {
 232         int idx;                /**< Which client desired? */
 233         int auth;               /**< Is client authenticated? */
 234         unsigned long pid;      /**< Process ID */
 235         unsigned long uid;      /**< User ID */
 236         unsigned long magic;    /**< Magic */
 237         unsigned long iocs;     /**< Ioctl count */
 238 };
 239
 240 enum drm_stat_type {
 241         _DRM_STAT_LOCK,
 242         _DRM_STAT_OPENS,
 243         _DRM_STAT_CLOSES,
 244         _DRM_STAT_IOCTLS,
 245         _DRM_STAT_LOCKS,
 246         _DRM_STAT_UNLOCKS,
 247         _DRM_STAT_VALUE,        /**< Generic value */
 248         _DRM_STAT_BYTE,         /**< Generic byte counter (1024bytes/K) */
 249         _DRM_STAT_COUNT,        /**< Generic non-byte counter (1000/k) */
 250
 251         _DRM_STAT_IRQ,          /**< IRQ */
 252         _DRM_STAT_PRIMARY,      /**< Primary DMA bytes */
 253         _DRM_STAT_SECONDARY,    /**< Secondary DMA bytes */
 254         _DRM_STAT_DMA,          /**< DMA */
 255         _DRM_STAT_SPECIAL,      /**< Special DMA (e.g., priority or polled) */
 256         _DRM_STAT_MISSED        /**< Missed DMA opportunity */
 257             /* Add to the *END* of the list */
 258 };
 259
 260 /**
 261  * DRM_IOCTL_GET_STATS ioctl argument type.
 262  */
 263 struct drm_stats {
 264         unsigned long count;
 265         struct {
 266                 unsigned long value;
 267                 enum drm_stat_type type;
 268         } data[15];
 269 };
 270
 271 /**
 272  * Hardware locking flags.
 273  */
 274 enum drm_lock_flags {
 275         _DRM_LOCK_READY = 0x01,      /**< Wait until hardware is ready for DMA */
 276         _DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
 277         _DRM_LOCK_FLUSH = 0x04,      /**< Flush this context's DMA queue first */
 278         _DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
 279         /* These *HALT* flags aren't supported yet
 280            -- they will be used to support the
 281            full-screen DGA-like mode. */
 282         _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
 283         _DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
 284 };
 285
 286 /**
 287  * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
 288  *
 289  * \sa drmGetLock() and drmUnlock().
 290  */
 291 struct drm_lock {
 292         int context;
 293         enum drm_lock_flags flags;
 294 };
 295
 296 /**
 297  * DMA flags
 298  *
 299  * \warning
 300  * These values \e must match xf86drm.h.
 301  *
 302  * \sa drm_dma.
 303  */
 304 enum drm_dma_flags {
 305         /* Flags for DMA buffer dispatch */
 306         _DRM_DMA_BLOCK = 0x01,        /**<
 307                                        * Block until buffer dispatched.
 308                                        *
 309                                        * \note The buffer may not yet have
 310                                        * been processed by the hardware --
 311                                        * getting a hardware lock with the
 312                                        * hardware quiescent will ensure
 313                                        * that the buffer has been
 314                                        * processed.
 315                                        */
 316         _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
 317         _DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
 318
 319         /* Flags for DMA buffer request */
 320         _DRM_DMA_WAIT = 0x10,         /**< Wait for free buffers */
 321         _DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
 322         _DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
 323 };
 324
 325 /**
 326  * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
 327  *
 328  * \sa drmAddBufs().
 329  */
 330 struct drm_buf_desc {
 331         int count;               /**< Number of buffers of this size */
 332         int size;                /**< Size in bytes */
 333         int low_mark;            /**< Low water mark */
 334         int high_mark;           /**< High water mark */
 335         enum {
 336                 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
 337                 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
 338                 _DRM_SG_BUFFER = 0x04,  /**< Scatter/gather memory buffer */
 339                 _DRM_FB_BUFFER = 0x08,  /**< Buffer is in frame buffer */
 340                 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
 341         } flags;
 342         unsigned long agp_start; /**<
 343                                   * Start address of where the AGP buffers are
 344                                   * in the AGP aperture
 345                                   */
 346 };
 347
 348 /**
 349  * DRM_IOCTL_INFO_BUFS ioctl argument type.
 350  */
 351 struct drm_buf_info {
 352         int count;              /**< Entries in list */
 353         struct drm_buf_desc *list;
 354 };
 355
 356 /**
 357  * DRM_IOCTL_FREE_BUFS ioctl argument type.
 358  */
 359 struct drm_buf_free {
 360         int count;
 361         int *list;
 362 };
 363
 364 /**
 365  * Buffer information
 366  *
 367  * \sa drm_buf_map.
 368  */
 369 struct drm_buf_pub {
 370         int idx;                       /**< Index into the master buffer list */
 371         int total;                     /**< Buffer size */
 372         int used;                      /**< Amount of buffer in use (for DMA) */
 373         void *address;         /**< Address of buffer */
 374 };
 375
 376 /**
 377  * DRM_IOCTL_MAP_BUFS ioctl argument type.
 378  */
 379 struct drm_buf_map {
 380         int count;              /**< Length of the buffer list */
 381 #ifdef __cplusplus
 382         void *virt;
 383 #else
 384         void *virtual;          /**< Mmap'd area in user-virtual */
 385 #endif
 386         struct drm_buf_pub *list;       /**< Buffer information */
 387 };
 388
 389 /**
 390  * DRM_IOCTL_DMA ioctl argument type.
 391  *
 392  * Indices here refer to the offset into the buffer list in drm_buf_get.
 393  *
 394  * \sa drmDMA().
 395  */
 396 struct drm_dma {
 397         int context;                      /**< Context handle */
 398         int send_count;                   /**< Number of buffers to send */
 399         int *send_indices;        /**< List of handles to buffers */
 400         int *send_sizes;                  /**< Lengths of data to send */
 401         enum drm_dma_flags flags;         /**< Flags */
 402         int request_count;                /**< Number of buffers requested */
 403         int request_size;                 /**< Desired size for buffers */
 404         int *request_indices;     /**< Buffer information */
 405         int *request_sizes;
 406         int granted_count;                /**< Number of buffers granted */
 407 };
 408
 409 enum drm_ctx_flags {
 410         _DRM_CONTEXT_PRESERVED = 0x01,
 411         _DRM_CONTEXT_2DONLY = 0x02
 412 };
 413
 414 /**
 415  * DRM_IOCTL_ADD_CTX ioctl argument type.
 416  *
 417  * \sa drmCreateContext() and drmDestroyContext().
 418  */
 419 struct drm_ctx {
 420         drm_context_t handle;
 421         enum drm_ctx_flags flags;
 422 };
 423
 424 /**
 425  * DRM_IOCTL_RES_CTX ioctl argument type.
 426  */
 427 struct drm_ctx_res {
 428         int count;
 429         struct drm_ctx *contexts;
 430 };
 431
 432 /**
 433  * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
 434  */
 435 struct drm_draw {
 436         drm_drawable_t handle;
 437 };
 438
 439 /**
 440  * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
 441  */
 442 typedef enum {
 443         DRM_DRAWABLE_CLIPRECTS
 444 } drm_drawable_info_type_t;
 445
 446 struct drm_update_draw {
 447         drm_drawable_t handle;
 448         unsigned int type;
 449         unsigned int num;
 450         unsigned long long data;
 451 };
 452
 453 /**
 454  * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
 455  */
 456 struct drm_auth {
 457         drm_magic_t magic;
 458 };
 459
 460 /**
 461  * DRM_IOCTL_IRQ_BUSID ioctl argument type.
 462  *
 463  * \sa drmGetInterruptFromBusID().
 464  */
 465 struct drm_irq_busid {
 466         int irq;        /**< IRQ number */
 467         int busnum;     /**< bus number */
 468         int devnum;     /**< device number */
 469         int funcnum;    /**< function number */
 470 };
 471
 472 enum drm_vblank_seq_type {
 473         _DRM_VBLANK_ABSOLUTE = 0x0,     /**< Wait for specific vblank sequence number */
 474         _DRM_VBLANK_RELATIVE = 0x1,     /**< Wait for given number of vblanks */
 475         /* bits 1-6 are reserved for high crtcs */
 476         _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
 477         _DRM_VBLANK_EVENT = 0x4000000,   /**< Send event instead of blocking */
 478         _DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
 479         _DRM_VBLANK_NEXTONMISS = 0x10000000,    /**< If missed, wait for next vblank */
 480         _DRM_VBLANK_SECONDARY = 0x20000000,     /**< Secondary display controller */
 481         _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
 482 };
 483 #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
 484
 485 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
 486 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
 487                                 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
 488
 489 struct drm_wait_vblank_request {
 490         enum drm_vblank_seq_type type;
 491         unsigned int sequence;
 492         unsigned long signal;
 493 };
 494
 495 struct drm_wait_vblank_reply {
 496         enum drm_vblank_seq_type type;
 497         unsigned int sequence;
 498         long tval_sec;
 499         long tval_usec;
 500 };
 501
 502 /**
 503  * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
 504  *
 505  * \sa drmWaitVBlank().
 506  */
 507 union drm_wait_vblank {
 508         struct drm_wait_vblank_request request;
 509         struct drm_wait_vblank_reply reply;
 510 };
 511
 512 #define _DRM_PRE_MODESET 1
 513 #define _DRM_POST_MODESET 2
 514
 515 /**
 516  * DRM_IOCTL_MODESET_CTL ioctl argument type
 517  *
 518  * \sa drmModesetCtl().
 519  */
 520 struct drm_modeset_ctl {
 521         __u32 crtc;
 522         __u32 cmd;
 523 };
 524
 525 /**
 526  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
 527  *
 528  * \sa drmAgpEnable().
 529  */
 530 struct drm_agp_mode {
 531         unsigned long mode;     /**< AGP mode */
 532 };
 533
 534 /**
 535  * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
 536  *
 537  * \sa drmAgpAlloc() and drmAgpFree().
 538  */
 539 struct drm_agp_buffer {
 540         unsigned long size;     /**< In bytes -- will round to page boundary */
 541         unsigned long handle;   /**< Used for binding / unbinding */
 542         unsigned long type;     /**< Type of memory to allocate */
 543         unsigned long physical; /**< Physical used by i810 */
 544 };
 545
 546 /**
 547  * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
 548  *
 549  * \sa drmAgpBind() and drmAgpUnbind().
 550  */
 551 struct drm_agp_binding {
 552         unsigned long handle;   /**< From drm_agp_buffer */
 553         unsigned long offset;   /**< In bytes -- will round to page boundary */
 554 };
 555
 556 /**
 557  * DRM_IOCTL_AGP_INFO ioctl argument type.
 558  *
 559  * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
 560  * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
 561  * drmAgpVendorId() and drmAgpDeviceId().
 562  */
 563 struct drm_agp_info {
 564         int agp_version_major;
 565         int agp_version_minor;
 566         unsigned long mode;
 567         unsigned long aperture_base;    /* physical address */
 568         unsigned long aperture_size;    /* bytes */
 569         unsigned long memory_allowed;   /* bytes */
 570         unsigned long memory_used;
 571
 572         /* PCI information */
 573         unsigned short id_vendor;
 574         unsigned short id_device;
 575 };
 576
 577 /**
 578  * DRM_IOCTL_SG_ALLOC ioctl argument type.
 579  */
 580 struct drm_scatter_gather {
 581         unsigned long size;     /**< In bytes -- will round to page boundary */
 582         unsigned long handle;   /**< Used for mapping / unmapping */
 583 };
 584
 585 /**
 586  * DRM_IOCTL_SET_VERSION ioctl argument type.
 587  */
 588 struct drm_set_version {
 589         int drm_di_major;
 590         int drm_di_minor;
 591         int drm_dd_major;
 592         int drm_dd_minor;
 593 };
 594
 595 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */
 596 struct drm_gem_close {
 597         /** Handle of the object to be closed. */
 598         __u32 handle;
 599         __u32 pad;
 600 };
 601
 602 /** DRM_IOCTL_GEM_FLINK ioctl argument type */
 603 struct drm_gem_flink {
 604         /** Handle for the object being named */
 605         __u32 handle;
 606
 607         /** Returned global name */
 608         __u32 name;
 609 };
 610
 611 /** DRM_IOCTL_GEM_OPEN ioctl argument type */
 612 struct drm_gem_open {
 613         /** Name of object being opened */
 614         __u32 name;
 615
 616         /** Returned handle for the object */
 617         __u32 handle;
 618
 619         /** Returned size of the object */
 620         __u64 size;
 621 };
 622
 623 #define DRM_CAP_DUMB_BUFFER             0x1
 624 #define DRM_CAP_VBLANK_HIGH_CRTC        0x2
 625 #define DRM_CAP_DUMB_PREFERRED_DEPTH    0x3
 626 #define DRM_CAP_DUMB_PREFER_SHADOW      0x4
 627 #define DRM_CAP_PRIME                   0x5
 628 #define  DRM_PRIME_CAP_IMPORT           0x1
 629 #define  DRM_PRIME_CAP_EXPORT           0x2
 630 #define DRM_CAP_TIMESTAMP_MONOTONIC     0x6
 631 #define DRM_CAP_ASYNC_PAGE_FLIP         0x7
 632 /*
 633  * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
 634  * combination for the hardware cursor. The intention is that a hardware
 635  * agnostic userspace can query a cursor plane size to use.
 636  *
 637  * Note that the cross-driver contract is to merely return a valid size;
 638  * drivers are free to attach another meaning on top, eg. i915 returns the
 639  * maximum plane size.
 640  */
 641 #define DRM_CAP_CURSOR_WIDTH            0x8
 642 #define DRM_CAP_CURSOR_HEIGHT           0x9
 643 #define DRM_CAP_ADDFB2_MODIFIERS        0x10
 644 #define DRM_CAP_PAGE_FLIP_TARGET        0x11
 645 #define DRM_CAP_CRTC_IN_VBLANK_EVENT    0x12
 646 #define DRM_CAP_SYNCOBJ         0x13
 647 #define DRM_CAP_SYNCOBJ_TIMELINE        0x14
 648
 649 /** DRM_IOCTL_GET_CAP ioctl argument type */
 650 struct drm_get_cap {
 651         __u64 capability;
 652         __u64 value;
 653 };
 654
 655 /**
 656  * DRM_CLIENT_CAP_STEREO_3D
 657  *
 658  * if set to 1, the DRM core will expose the stereo 3D capabilities of the
 659  * monitor by advertising the supported 3D layouts in the flags of struct
 660  * drm_mode_modeinfo.
 661  */
 662 #define DRM_CLIENT_CAP_STEREO_3D        1
 663
 664 /**
 665  * DRM_CLIENT_CAP_UNIVERSAL_PLANES
 666  *
 667  * If set to 1, the DRM core will expose all planes (overlay, primary, and
 668  * cursor) to userspace.
 669  */
 670 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES  2
 671
 672 /**
 673  * DRM_CLIENT_CAP_ATOMIC
 674  *
 675  * If set to 1, the DRM core will expose atomic properties to userspace
 676  */
 677 #define DRM_CLIENT_CAP_ATOMIC   3
 678
 679 /**
 680  * DRM_CLIENT_CAP_ASPECT_RATIO
 681  *
 682  * If set to 1, the DRM core will provide aspect ratio information in modes.
 683  */
 684 #define DRM_CLIENT_CAP_ASPECT_RATIO    4
 685
 686 /**
 687  * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
 688  *
 689  * If set to 1, the DRM core will expose special connectors to be used for
 690  * writing back to memory the scene setup in the commit. Depends on client
 691  * also supporting DRM_CLIENT_CAP_ATOMIC
 692  */
 693 #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS     5
 694
 695 /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
 696 struct drm_set_client_cap {
 697         __u64 capability;
 698         __u64 value;
 699 };
 700
 701 #define DRM_RDWR O_RDWR
 702 #define DRM_CLOEXEC O_CLOEXEC
 703 struct drm_prime_handle {
 704         __u32 handle;
 705
 706         /** Flags.. only applicable for handle->fd */
 707         __u32 flags;
 708
 709         /** Returned dmabuf file descriptor */
 710         __s32 fd;
 711 };
 712
 713 struct drm_syncobj_create {
 714         __u32 handle;
 715 #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
 716         __u32 flags;
 717 };
 718
 719 struct drm_syncobj_destroy {
 720         __u32 handle;
 721         __u32 pad;
 722 };
 723
 724 #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
 725 #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
 726 struct drm_syncobj_handle {
 727         __u32 handle;
 728         __u32 flags;
 729
 730         __s32 fd;
 731         __u32 pad;
 732 };
 733
 734 struct drm_syncobj_transfer {
 735         __u32 src_handle;
 736         __u32 dst_handle;
 737         __u64 src_point;
 738         __u64 dst_point;
 739         __u32 flags;
 740         __u32 pad;
 741 };
 742
 743 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
 744 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
 745 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
 746 struct drm_syncobj_wait {
 747         __u64 handles;
 748         /* absolute timeout */
 749         __s64 timeout_nsec;
 750         __u32 count_handles;
 751         __u32 flags;
 752         __u32 first_signaled; /* only valid when not waiting all */
 753         __u32 pad;
 754 };
 755
 756 struct drm_syncobj_timeline_wait {
 757         __u64 handles;
 758         /* wait on specific timeline point for every handles*/
 759         __u64 points;
 760         /* absolute timeout */
 761         __s64 timeout_nsec;
 762         __u32 count_handles;
 763         __u32 flags;
 764         __u32 first_signaled; /* only valid when not waiting all */
 765         __u32 pad;
 766 };
 767
 768
 769 struct drm_syncobj_array {
 770         __u64 handles;
 771         __u32 count_handles;
 772         __u32 pad;
 773 };
 774
 775 struct drm_syncobj_timeline_array {
 776         __u64 handles;
 777         __u64 points;
 778         __u32 count_handles;
 779         __u32 pad;
 780 };
 781
 782
 783 /* Query current scanout sequence number */
 784 struct drm_crtc_get_sequence {
 785         __u32 crtc_id;          /* requested crtc_id */
 786         __u32 active;           /* return: crtc output is active */
 787         __u64 sequence;         /* return: most recent vblank sequence */
 788         __s64 sequence_ns;      /* return: most recent time of first pixel out */
 789 };
 790
 791 /* Queue event to be delivered at specified sequence. Time stamp marks
 792  * when the first pixel of the refresh cycle leaves the display engine
 793  * for the display
 794  */
 795 #define DRM_CRTC_SEQUENCE_RELATIVE              0x00000001      /* sequence is relative to current */
 796 #define DRM_CRTC_SEQUENCE_NEXT_ON_MISS          0x00000002      /* Use next sequence if we've missed */
 797
 798 struct drm_crtc_queue_sequence {
 799         __u32 crtc_id;
 800         __u32 flags;
 801         __u64 sequence;         /* on input, target sequence. on output, actual sequence */
 802         __u64 user_data;        /* user data passed to event */
 803 };
 804
 805 #if defined(__cplusplus)
 806 }
 807 #endif
 808
 809 #include "drm_mode.h"
 810
 811 #if defined(__cplusplus)
 812 extern "C" {
 813 #endif
 814
 815 #define DRM_IOCTL_BASE                  'd'
 816 #define DRM_IO(nr)                      _IO(DRM_IOCTL_BASE,nr)
 817 #define DRM_IOR(nr,type)                _IOR(DRM_IOCTL_BASE,nr,type)
 818 #define DRM_IOW(nr,type)                _IOW(DRM_IOCTL_BASE,nr,type)
 819 #define DRM_IOWR(nr,type)               _IOWR(DRM_IOCTL_BASE,nr,type)
 820
 821 #define DRM_IOCTL_VERSION               DRM_IOWR(0x00, struct drm_version)
 822 #define DRM_IOCTL_GET_UNIQUE            DRM_IOWR(0x01, struct drm_unique)
 823 #define DRM_IOCTL_GET_MAGIC             DRM_IOR( 0x02, struct drm_auth)
 824 #define DRM_IOCTL_IRQ_BUSID             DRM_IOWR(0x03, struct drm_irq_busid)
 825 #define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, struct drm_map)
 826 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
 827 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
 828 #define DRM_IOCTL_SET_VERSION           DRM_IOWR(0x07, struct drm_set_version)
 829 #define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
 830 #define DRM_IOCTL_GEM_CLOSE             DRM_IOW (0x09, struct drm_gem_close)
 831 #define DRM_IOCTL_GEM_FLINK             DRM_IOWR(0x0a, struct drm_gem_flink)
 832 #define DRM_IOCTL_GEM_OPEN              DRM_IOWR(0x0b, struct drm_gem_open)
 833 #define DRM_IOCTL_GET_CAP               DRM_IOWR(0x0c, struct drm_get_cap)
 834 #define DRM_IOCTL_SET_CLIENT_CAP        DRM_IOW( 0x0d, struct drm_set_client_cap)
 835
 836 #define DRM_IOCTL_SET_UNIQUE            DRM_IOW( 0x10, struct drm_unique)
 837 #define DRM_IOCTL_AUTH_MAGIC            DRM_IOW( 0x11, struct drm_auth)
 838 #define DRM_IOCTL_BLOCK                 DRM_IOWR(0x12, struct drm_block)
 839 #define DRM_IOCTL_UNBLOCK               DRM_IOWR(0x13, struct drm_block)
 840 #define DRM_IOCTL_CONTROL               DRM_IOW( 0x14, struct drm_control)
 841 #define DRM_IOCTL_ADD_MAP               DRM_IOWR(0x15, struct drm_map)
 842 #define DRM_IOCTL_ADD_BUFS              DRM_IOWR(0x16, struct drm_buf_desc)
 843 #define DRM_IOCTL_MARK_BUFS             DRM_IOW( 0x17, struct drm_buf_desc)
 844 #define DRM_IOCTL_INFO_BUFS             DRM_IOWR(0x18, struct drm_buf_info)
 845 #define DRM_IOCTL_MAP_BUFS              DRM_IOWR(0x19, struct drm_buf_map)
 846 #define DRM_IOCTL_FREE_BUFS             DRM_IOW( 0x1a, struct drm_buf_free)
 847
 848 #define DRM_IOCTL_RM_MAP                DRM_IOW( 0x1b, struct drm_map)
 849
 850 #define DRM_IOCTL_SET_SAREA_CTX         DRM_IOW( 0x1c, struct drm_ctx_priv_map)
 851 #define DRM_IOCTL_GET_SAREA_CTX         DRM_IOWR(0x1d, struct drm_ctx_priv_map)
 852
 853 #define DRM_IOCTL_SET_MASTER            DRM_IO(0x1e)
 854 #define DRM_IOCTL_DROP_MASTER           DRM_IO(0x1f)
 855
 856 #define DRM_IOCTL_ADD_CTX               DRM_IOWR(0x20, struct drm_ctx)
 857 #define DRM_IOCTL_RM_CTX                DRM_IOWR(0x21, struct drm_ctx)
 858 #define DRM_IOCTL_MOD_CTX               DRM_IOW( 0x22, struct drm_ctx)
 859 #define DRM_IOCTL_GET_CTX               DRM_IOWR(0x23, struct drm_ctx)
 860 #define DRM_IOCTL_SWITCH_CTX            DRM_IOW( 0x24, struct drm_ctx)
 861 #define DRM_IOCTL_NEW_CTX               DRM_IOW( 0x25, struct drm_ctx)
 862 #define DRM_IOCTL_RES_CTX               DRM_IOWR(0x26, struct drm_ctx_res)
 863 #define DRM_IOCTL_ADD_DRAW              DRM_IOWR(0x27, struct drm_draw)
 864 #define DRM_IOCTL_RM_DRAW               DRM_IOWR(0x28, struct drm_draw)
 865 #define DRM_IOCTL_DMA                   DRM_IOWR(0x29, struct drm_dma)
 866 #define DRM_IOCTL_LOCK                  DRM_IOW( 0x2a, struct drm_lock)
 867 #define DRM_IOCTL_UNLOCK                DRM_IOW( 0x2b, struct drm_lock)
 868 #define DRM_IOCTL_FINISH                DRM_IOW( 0x2c, struct drm_lock)
 869
 870 #define DRM_IOCTL_PRIME_HANDLE_TO_FD    DRM_IOWR(0x2d, struct drm_prime_handle)
 871 #define DRM_IOCTL_PRIME_FD_TO_HANDLE    DRM_IOWR(0x2e, struct drm_prime_handle)
 872
 873 #define DRM_IOCTL_AGP_ACQUIRE           DRM_IO(  0x30)
 874 #define DRM_IOCTL_AGP_RELEASE           DRM_IO(  0x31)
 875 #define DRM_IOCTL_AGP_ENABLE            DRM_IOW( 0x32, struct drm_agp_mode)
 876 #define DRM_IOCTL_AGP_INFO              DRM_IOR( 0x33, struct drm_agp_info)
 877 #define DRM_IOCTL_AGP_ALLOC             DRM_IOWR(0x34, struct drm_agp_buffer)
 878 #define DRM_IOCTL_AGP_FREE              DRM_IOW( 0x35, struct drm_agp_buffer)
 879 #define DRM_IOCTL_AGP_BIND              DRM_IOW( 0x36, struct drm_agp_binding)
 880 #define DRM_IOCTL_AGP_UNBIND            DRM_IOW( 0x37, struct drm_agp_binding)
 881
 882 #define DRM_IOCTL_SG_ALLOC              DRM_IOWR(0x38, struct drm_scatter_gather)
 883 #define DRM_IOCTL_SG_FREE               DRM_IOW( 0x39, struct drm_scatter_gather)
 884
 885 #define DRM_IOCTL_WAIT_VBLANK           DRM_IOWR(0x3a, union drm_wait_vblank)
 886
 887 #define DRM_IOCTL_CRTC_GET_SEQUENCE     DRM_IOWR(0x3b, struct drm_crtc_get_sequence)
 888 #define DRM_IOCTL_CRTC_QUEUE_SEQUENCE   DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)
 889
 890 #define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, struct drm_update_draw)
 891
 892 #define DRM_IOCTL_MODE_GETRESOURCES     DRM_IOWR(0xA0, struct drm_mode_card_res)
 893 #define DRM_IOCTL_MODE_GETCRTC          DRM_IOWR(0xA1, struct drm_mode_crtc)
 894 #define DRM_IOCTL_MODE_SETCRTC          DRM_IOWR(0xA2, struct drm_mode_crtc)
 895 #define DRM_IOCTL_MODE_CURSOR           DRM_IOWR(0xA3, struct drm_mode_cursor)
 896 #define DRM_IOCTL_MODE_GETGAMMA         DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
 897 #define DRM_IOCTL_MODE_SETGAMMA         DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
 898 #define DRM_IOCTL_MODE_GETENCODER       DRM_IOWR(0xA6, struct drm_mode_get_encoder)
 899 #define DRM_IOCTL_MODE_GETCONNECTOR     DRM_IOWR(0xA7, struct drm_mode_get_connector)
 900 #define DRM_IOCTL_MODE_ATTACHMODE       DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
 901 #define DRM_IOCTL_MODE_DETACHMODE       DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
 902
 903 #define DRM_IOCTL_MODE_GETPROPERTY      DRM_IOWR(0xAA, struct drm_mode_get_property)
 904 #define DRM_IOCTL_MODE_SETPROPERTY      DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
 905 #define DRM_IOCTL_MODE_GETPROPBLOB      DRM_IOWR(0xAC, struct drm_mode_get_blob)
 906 #define DRM_IOCTL_MODE_GETFB            DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
 907 #define DRM_IOCTL_MODE_ADDFB            DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
 908 #define DRM_IOCTL_MODE_RMFB             DRM_IOWR(0xAF, unsigned int)
 909 #define DRM_IOCTL_MODE_PAGE_FLIP        DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
 910 #define DRM_IOCTL_MODE_DIRTYFB          DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
 911
 912 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
 913 #define DRM_IOCTL_MODE_MAP_DUMB    DRM_IOWR(0xB3, struct drm_mode_map_dumb)
 914 #define DRM_IOCTL_MODE_DESTROY_DUMB    DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
 915 #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
 916 #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
 917 #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
 918 #define DRM_IOCTL_MODE_ADDFB2           DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
 919 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES        DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
 920 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY  DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
 921 #define DRM_IOCTL_MODE_CURSOR2          DRM_IOWR(0xBB, struct drm_mode_cursor2)
 922 #define DRM_IOCTL_MODE_ATOMIC           DRM_IOWR(0xBC, struct drm_mode_atomic)
 923 #define DRM_IOCTL_MODE_CREATEPROPBLOB   DRM_IOWR(0xBD, struct drm_mode_create_blob)
 924 #define DRM_IOCTL_MODE_DESTROYPROPBLOB  DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
 925
 926 #define DRM_IOCTL_SYNCOBJ_CREATE        DRM_IOWR(0xBF, struct drm_syncobj_create)
 927 #define DRM_IOCTL_SYNCOBJ_DESTROY       DRM_IOWR(0xC0, struct drm_syncobj_destroy)
 928 #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD  DRM_IOWR(0xC1, struct drm_syncobj_handle)
 929 #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE  DRM_IOWR(0xC2, struct drm_syncobj_handle)
 930 #define DRM_IOCTL_SYNCOBJ_WAIT          DRM_IOWR(0xC3, struct drm_syncobj_wait)
 931 #define DRM_IOCTL_SYNCOBJ_RESET         DRM_IOWR(0xC4, struct drm_syncobj_array)
 932 #define DRM_IOCTL_SYNCOBJ_SIGNAL        DRM_IOWR(0xC5, struct drm_syncobj_array)
 933
 934 #define DRM_IOCTL_MODE_CREATE_LEASE     DRM_IOWR(0xC6, struct drm_mode_create_lease)
 935 #define DRM_IOCTL_MODE_LIST_LESSEES     DRM_IOWR(0xC7, struct drm_mode_list_lessees)
 936 #define DRM_IOCTL_MODE_GET_LEASE        DRM_IOWR(0xC8, struct drm_mode_get_lease)
 937 #define DRM_IOCTL_MODE_REVOKE_LEASE     DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
 938
 939 #define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
 940 #define DRM_IOCTL_SYNCOBJ_QUERY         DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
 941 #define DRM_IOCTL_SYNCOBJ_TRANSFER      DRM_IOWR(0xCC, struct drm_syncobj_transfer)
 942 #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL       DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
 943
 944 /**
 945  * Device specific ioctls should only be in their respective headers
 946  * The device specific ioctl range is from 0x40 to 0x9f.
 947  * Generic IOCTLS restart at 0xA0.
 948  *
 949  * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
 950  * drmCommandReadWrite().
 951  */
 952 #define DRM_COMMAND_BASE                0x40
 953 #define DRM_COMMAND_END                 0xA0
 954
 955 /**
 956  * Header for events written back to userspace on the drm fd.  The
 957  * type defines the type of event, the length specifies the total
 958  * length of the event (including the header), and user_data is
 959  * typically a 64 bit value passed with the ioctl that triggered the
 960  * event.  A read on the drm fd will always only return complete
 961  * events, that is, if for example the read buffer is 100 bytes, and
 962  * there are two 64 byte events pending, only one will be returned.
 963  *
 964  * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
 965  * up are chipset specific.
 966  */
 967 struct drm_event {
 968         __u32 type;
 969         __u32 length;
 970 };
 971
 972 #define DRM_EVENT_VBLANK 0x01
 973 #define DRM_EVENT_FLIP_COMPLETE 0x02
 974 #define DRM_EVENT_CRTC_SEQUENCE 0x03
 975
 976 struct drm_event_vblank {
 977         struct drm_event base;
 978         __u64 user_data;
 979         __u32 tv_sec;
 980         __u32 tv_usec;
 981         __u32 sequence;
 982         __u32 crtc_id; /* 0 on older kernels that do not support this */
 983 };
 984
 985 /* Event delivered at sequence. Time stamp marks when the first pixel
 986  * of the refresh cycle leaves the display engine for the display
 987  */
 988 struct drm_event_crtc_sequence {
 989         struct drm_event        base;
 990         __u64                   user_data;
 991         __s64                   time_ns;
 992         __u64                   sequence;
 993 };
 994
 995 /* typedef area */
 996 typedef struct drm_clip_rect drm_clip_rect_t;
 997 typedef struct drm_drawable_info drm_drawable_info_t;
 998 typedef struct drm_tex_region drm_tex_region_t;
 999 typedef struct drm_hw_lock drm_hw_lock_t;
1000 typedef struct drm_version drm_version_t;
1001 typedef struct drm_unique drm_unique_t;
1002 typedef struct drm_list drm_list_t;
1003 typedef struct drm_block drm_block_t;
1004 typedef struct drm_control drm_control_t;
1005 typedef enum drm_map_type drm_map_type_t;
1006 typedef enum drm_map_flags drm_map_flags_t;
1007 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
1008 typedef struct drm_map drm_map_t;
1009 typedef struct drm_client drm_client_t;
1010 typedef enum drm_stat_type drm_stat_type_t;
1011 typedef struct drm_stats drm_stats_t;
1012 typedef enum drm_lock_flags drm_lock_flags_t;
1013 typedef struct drm_lock drm_lock_t;
1014 typedef enum drm_dma_flags drm_dma_flags_t;
1015 typedef struct drm_buf_desc drm_buf_desc_t;
1016 typedef struct drm_buf_info drm_buf_info_t;
1017 typedef struct drm_buf_free drm_buf_free_t;
1018 typedef struct drm_buf_pub drm_buf_pub_t;
1019 typedef struct drm_buf_map drm_buf_map_t;
1020 typedef struct drm_dma drm_dma_t;
1021 typedef union drm_wait_vblank drm_wait_vblank_t;
1022 typedef struct drm_agp_mode drm_agp_mode_t;
1023 typedef enum drm_ctx_flags drm_ctx_flags_t;
1024 typedef struct drm_ctx drm_ctx_t;
1025 typedef struct drm_ctx_res drm_ctx_res_t;
1026 typedef struct drm_draw drm_draw_t;
1027 typedef struct drm_update_draw drm_update_draw_t;
1028 typedef struct drm_auth drm_auth_t;
1029 typedef struct drm_irq_busid drm_irq_busid_t;
1030 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1031
1032 typedef struct drm_agp_buffer drm_agp_buffer_t;
1033 typedef struct drm_agp_binding drm_agp_binding_t;
1034 typedef struct drm_agp_info drm_agp_info_t;
1035 typedef struct drm_scatter_gather drm_scatter_gather_t;
1036 typedef struct drm_set_version drm_set_version_t;
1037
1038 #if defined(__cplusplus)
1039 }
1040 #endif
1041
1042 #endif