2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 #if defined(__cplusplus)
36 /* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
41 * DOC: uevents generated by i915 on it's device node
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * the GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62 #define I915_ERROR_UEVENT "ERROR"
63 #define I915_RESET_UEVENT "RESET"
66 * i915_user_extension: Base class for defining a chain of extensions
68 * Many interfaces need to grow over time. In most cases we can simply
69 * extend the struct and have userspace pass in more data. Another option,
70 * as demonstrated by Vulkan's approach to providing extensions for forward
71 * and backward compatibility, is to use a list of optional structs to
72 * provide those extra details.
74 * The key advantage to using an extension chain is that it allows us to
75 * redefine the interface more easily than an ever growing struct of
76 * increasing complexity, and for large parts of that interface to be
77 * entirely optional. The downside is more pointer chasing; chasing across
78 * the boundary with pointers encapsulated inside u64.
80 struct i915_user_extension
{
83 __u32 flags
; /* All undefined bits must be zero. */
84 __u32 rsvd
[4]; /* Reserved for future use; must be zero. */
88 * MOCS indexes used for GPU surfaces, defining the cacheability of the
89 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
91 enum i915_mocs_table_index
{
93 * Not cached anywhere, coherency between CPU and GPU accesses is
98 * Cacheability and coherency controlled by the kernel automatically
99 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
100 * usage of the surface (used for display scanout or not).
104 * Cached in all GPU caches available on the platform.
105 * Coherency between CPU and GPU accesses to the surface is not
106 * guaranteed without extra synchronization.
112 * Different engines serve different roles, and there may be more than one
113 * engine serving each role. enum drm_i915_gem_engine_class provides a
114 * classification of the role of the engine, which may be used when requesting
115 * operations to be performed on a certain subset of engines, or for providing
116 * information about that group.
118 enum drm_i915_gem_engine_class
{
119 I915_ENGINE_CLASS_RENDER
= 0,
120 I915_ENGINE_CLASS_COPY
= 1,
121 I915_ENGINE_CLASS_VIDEO
= 2,
122 I915_ENGINE_CLASS_VIDEO_ENHANCE
= 3,
124 /* should be kept compact */
126 I915_ENGINE_CLASS_INVALID
= -1
130 * There may be more than one engine fulfilling any role within the system.
131 * Each engine of a class is given a unique instance number and therefore
132 * any engine can be specified by its class:instance tuplet. APIs that allow
133 * access to any engine in the system will use struct i915_engine_class_instance
134 * for this identification.
136 struct i915_engine_class_instance
{
137 __u16 engine_class
; /* see enum drm_i915_gem_engine_class */
138 __u16 engine_instance
;
139 #define I915_ENGINE_CLASS_INVALID_NONE -1
140 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
144 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
148 enum drm_i915_pmu_engine_sample
{
149 I915_SAMPLE_BUSY
= 0,
150 I915_SAMPLE_WAIT
= 1,
154 #define I915_PMU_SAMPLE_BITS (4)
155 #define I915_PMU_SAMPLE_MASK (0xf)
156 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
157 #define I915_PMU_CLASS_SHIFT \
158 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
160 #define __I915_PMU_ENGINE(class, instance, sample) \
161 ((class) << I915_PMU_CLASS_SHIFT | \
162 (instance) << I915_PMU_SAMPLE_BITS | \
165 #define I915_PMU_ENGINE_BUSY(class, instance) \
166 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
168 #define I915_PMU_ENGINE_WAIT(class, instance) \
169 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
171 #define I915_PMU_ENGINE_SEMA(class, instance) \
172 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
174 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
176 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
177 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
178 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
179 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
181 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
183 /* Each region is a minimum of 16k, and there are at most 255 of them.
185 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
186 * of chars for next/prev indices */
187 #define I915_LOG_MIN_TEX_REGION_SIZE 14
189 typedef struct _drm_i915_init
{
191 I915_INIT_DMA
= 0x01,
192 I915_CLEANUP_DMA
= 0x02,
193 I915_RESUME_DMA
= 0x03
195 unsigned int mmio_offset
;
196 int sarea_priv_offset
;
197 unsigned int ring_start
;
198 unsigned int ring_end
;
199 unsigned int ring_size
;
200 unsigned int front_offset
;
201 unsigned int back_offset
;
202 unsigned int depth_offset
;
206 unsigned int pitch_bits
;
207 unsigned int back_pitch
;
208 unsigned int depth_pitch
;
210 unsigned int chipset
;
213 typedef struct _drm_i915_sarea
{
214 struct drm_tex_region texList
[I915_NR_TEX_REGIONS
+ 1];
215 int last_upload
; /* last time texture was uploaded */
216 int last_enqueue
; /* last time a buffer was enqueued */
217 int last_dispatch
; /* age of the most recently dispatched buffer */
218 int ctxOwner
; /* last context to upload state */
220 int pf_enabled
; /* is pageflipping allowed? */
222 int pf_current_page
; /* which buffer is being displayed? */
223 int perf_boxes
; /* performance boxes to be displayed */
224 int width
, height
; /* screen size in pixels */
226 drm_handle_t front_handle
;
230 drm_handle_t back_handle
;
234 drm_handle_t depth_handle
;
238 drm_handle_t tex_handle
;
241 int log_tex_granularity
;
243 int rotation
; /* 0, 90, 180 or 270 */
247 int virtualX
, virtualY
;
249 unsigned int front_tiled
;
250 unsigned int back_tiled
;
251 unsigned int depth_tiled
;
252 unsigned int rotated_tiled
;
253 unsigned int rotated2_tiled
;
264 /* fill out some space for old userspace triple buffer */
265 drm_handle_t unused_handle
;
266 __u32 unused1
, unused2
, unused3
;
268 /* buffer object handles for static buffers. May change
269 * over the lifetime of the client.
271 __u32 front_bo_handle
;
272 __u32 back_bo_handle
;
273 __u32 unused_bo_handle
;
274 __u32 depth_bo_handle
;
278 /* due to userspace building against these headers we need some compat here */
279 #define planeA_x pipeA_x
280 #define planeA_y pipeA_y
281 #define planeA_w pipeA_w
282 #define planeA_h pipeA_h
283 #define planeB_x pipeB_x
284 #define planeB_y pipeB_y
285 #define planeB_w pipeB_w
286 #define planeB_h pipeB_h
288 /* Flags for perf_boxes
290 #define I915_BOX_RING_EMPTY 0x1
291 #define I915_BOX_FLIP 0x2
292 #define I915_BOX_WAIT 0x4
293 #define I915_BOX_TEXTURE_LOAD 0x8
294 #define I915_BOX_LOST_CONTEXT 0x10
297 * i915 specific ioctls.
299 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
300 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
301 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
303 #define DRM_I915_INIT 0x00
304 #define DRM_I915_FLUSH 0x01
305 #define DRM_I915_FLIP 0x02
306 #define DRM_I915_BATCHBUFFER 0x03
307 #define DRM_I915_IRQ_EMIT 0x04
308 #define DRM_I915_IRQ_WAIT 0x05
309 #define DRM_I915_GETPARAM 0x06
310 #define DRM_I915_SETPARAM 0x07
311 #define DRM_I915_ALLOC 0x08
312 #define DRM_I915_FREE 0x09
313 #define DRM_I915_INIT_HEAP 0x0a
314 #define DRM_I915_CMDBUFFER 0x0b
315 #define DRM_I915_DESTROY_HEAP 0x0c
316 #define DRM_I915_SET_VBLANK_PIPE 0x0d
317 #define DRM_I915_GET_VBLANK_PIPE 0x0e
318 #define DRM_I915_VBLANK_SWAP 0x0f
319 #define DRM_I915_HWS_ADDR 0x11
320 #define DRM_I915_GEM_INIT 0x13
321 #define DRM_I915_GEM_EXECBUFFER 0x14
322 #define DRM_I915_GEM_PIN 0x15
323 #define DRM_I915_GEM_UNPIN 0x16
324 #define DRM_I915_GEM_BUSY 0x17
325 #define DRM_I915_GEM_THROTTLE 0x18
326 #define DRM_I915_GEM_ENTERVT 0x19
327 #define DRM_I915_GEM_LEAVEVT 0x1a
328 #define DRM_I915_GEM_CREATE 0x1b
329 #define DRM_I915_GEM_PREAD 0x1c
330 #define DRM_I915_GEM_PWRITE 0x1d
331 #define DRM_I915_GEM_MMAP 0x1e
332 #define DRM_I915_GEM_SET_DOMAIN 0x1f
333 #define DRM_I915_GEM_SW_FINISH 0x20
334 #define DRM_I915_GEM_SET_TILING 0x21
335 #define DRM_I915_GEM_GET_TILING 0x22
336 #define DRM_I915_GEM_GET_APERTURE 0x23
337 #define DRM_I915_GEM_MMAP_GTT 0x24
338 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
339 #define DRM_I915_GEM_MADVISE 0x26
340 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
341 #define DRM_I915_OVERLAY_ATTRS 0x28
342 #define DRM_I915_GEM_EXECBUFFER2 0x29
343 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
344 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
345 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
346 #define DRM_I915_GEM_WAIT 0x2c
347 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
348 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
349 #define DRM_I915_GEM_SET_CACHING 0x2f
350 #define DRM_I915_GEM_GET_CACHING 0x30
351 #define DRM_I915_REG_READ 0x31
352 #define DRM_I915_GET_RESET_STATS 0x32
353 #define DRM_I915_GEM_USERPTR 0x33
354 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
355 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
356 #define DRM_I915_PERF_OPEN 0x36
357 #define DRM_I915_PERF_ADD_CONFIG 0x37
358 #define DRM_I915_PERF_REMOVE_CONFIG 0x38
359 #define DRM_I915_QUERY 0x39
360 #define DRM_I915_GEM_VM_CREATE 0x3a
361 #define DRM_I915_GEM_VM_DESTROY 0x3b
362 /* Must be kept compact -- no holes */
364 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
365 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
366 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
367 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
368 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
369 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
370 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
371 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
372 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
373 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
374 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
375 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
376 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
377 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
378 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
379 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
380 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
381 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
382 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
383 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
384 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
385 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
386 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
387 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
388 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
389 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
390 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
391 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
392 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
393 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
394 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
395 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
396 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
397 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
398 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
399 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
400 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
401 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
402 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
403 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
404 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
405 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
406 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
407 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
408 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
409 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
410 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
411 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
412 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
413 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
414 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
415 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
416 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
417 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
418 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
419 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
420 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
421 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
422 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
423 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
425 /* Allow drivers to submit batchbuffers directly to hardware, relying
426 * on the security mechanisms provided by hardware.
428 typedef struct drm_i915_batchbuffer
{
429 int start
; /* agp offset */
430 int used
; /* nr bytes in use */
431 int DR1
; /* hw flags for GFX_OP_DRAWRECT_INFO */
432 int DR4
; /* window origin for GFX_OP_DRAWRECT_INFO */
433 int num_cliprects
; /* mulitpass with multiple cliprects? */
434 struct drm_clip_rect
*cliprects
; /* pointer to userspace cliprects */
435 } drm_i915_batchbuffer_t
;
437 /* As above, but pass a pointer to userspace buffer which can be
438 * validated by the kernel prior to sending to hardware.
440 typedef struct _drm_i915_cmdbuffer
{
441 char *buf
; /* pointer to userspace command buffer */
442 int sz
; /* nr bytes in buf */
443 int DR1
; /* hw flags for GFX_OP_DRAWRECT_INFO */
444 int DR4
; /* window origin for GFX_OP_DRAWRECT_INFO */
445 int num_cliprects
; /* mulitpass with multiple cliprects? */
446 struct drm_clip_rect
*cliprects
; /* pointer to userspace cliprects */
447 } drm_i915_cmdbuffer_t
;
449 /* Userspace can request & wait on irq's:
451 typedef struct drm_i915_irq_emit
{
453 } drm_i915_irq_emit_t
;
455 typedef struct drm_i915_irq_wait
{
457 } drm_i915_irq_wait_t
;
460 * Different modes of per-process Graphics Translation Table,
461 * see I915_PARAM_HAS_ALIASING_PPGTT
463 #define I915_GEM_PPGTT_NONE 0
464 #define I915_GEM_PPGTT_ALIASING 1
465 #define I915_GEM_PPGTT_FULL 2
467 /* Ioctl to query kernel params:
469 #define I915_PARAM_IRQ_ACTIVE 1
470 #define I915_PARAM_ALLOW_BATCHBUFFER 2
471 #define I915_PARAM_LAST_DISPATCH 3
472 #define I915_PARAM_CHIPSET_ID 4
473 #define I915_PARAM_HAS_GEM 5
474 #define I915_PARAM_NUM_FENCES_AVAIL 6
475 #define I915_PARAM_HAS_OVERLAY 7
476 #define I915_PARAM_HAS_PAGEFLIPPING 8
477 #define I915_PARAM_HAS_EXECBUF2 9
478 #define I915_PARAM_HAS_BSD 10
479 #define I915_PARAM_HAS_BLT 11
480 #define I915_PARAM_HAS_RELAXED_FENCING 12
481 #define I915_PARAM_HAS_COHERENT_RINGS 13
482 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
483 #define I915_PARAM_HAS_RELAXED_DELTA 15
484 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
485 #define I915_PARAM_HAS_LLC 17
486 #define I915_PARAM_HAS_ALIASING_PPGTT 18
487 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
488 #define I915_PARAM_HAS_SEMAPHORES 20
489 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
490 #define I915_PARAM_HAS_VEBOX 22
491 #define I915_PARAM_HAS_SECURE_BATCHES 23
492 #define I915_PARAM_HAS_PINNED_BATCHES 24
493 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
494 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
495 #define I915_PARAM_HAS_WT 27
496 #define I915_PARAM_CMD_PARSER_VERSION 28
497 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
498 #define I915_PARAM_MMAP_VERSION 30
499 #define I915_PARAM_HAS_BSD2 31
500 #define I915_PARAM_REVISION 32
501 #define I915_PARAM_SUBSLICE_TOTAL 33
502 #define I915_PARAM_EU_TOTAL 34
503 #define I915_PARAM_HAS_GPU_RESET 35
504 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
505 #define I915_PARAM_HAS_EXEC_SOFTPIN 37
506 #define I915_PARAM_HAS_POOLED_EU 38
507 #define I915_PARAM_MIN_EU_IN_POOL 39
508 #define I915_PARAM_MMAP_GTT_VERSION 40
511 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
512 * priorities and the driver will attempt to execute batches in priority order.
513 * The param returns a capability bitmask, nonzero implies that the scheduler
514 * is enabled, with different features present according to the mask.
516 * The initial priority for each batch is supplied by the context and is
517 * controlled via I915_CONTEXT_PARAM_PRIORITY.
519 #define I915_PARAM_HAS_SCHEDULER 41
520 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
521 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
522 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
523 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
524 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
526 #define I915_PARAM_HUC_STATUS 42
528 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
529 * synchronisation with implicit fencing on individual objects.
530 * See EXEC_OBJECT_ASYNC.
532 #define I915_PARAM_HAS_EXEC_ASYNC 43
534 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
535 * both being able to pass in a sync_file fd to wait upon before executing,
536 * and being able to return a new sync_file fd that is signaled when the
537 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
539 #define I915_PARAM_HAS_EXEC_FENCE 44
541 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
542 * user specified bufffers for post-mortem debugging of GPU hangs. See
543 * EXEC_OBJECT_CAPTURE.
545 #define I915_PARAM_HAS_EXEC_CAPTURE 45
547 #define I915_PARAM_SLICE_MASK 46
549 /* Assuming it's uniform for each slice, this queries the mask of subslices
550 * per-slice for this system.
552 #define I915_PARAM_SUBSLICE_MASK 47
555 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
556 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
558 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
560 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
561 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
563 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
566 * Query whether every context (both per-file default and user created) is
567 * isolated (insofar as HW supports). If this parameter is not true, then
568 * freshly created contexts may inherit values from an existing context,
569 * rather than default HW values. If true, it also ensures (insofar as HW
570 * supports) that all state set by this context will not leak to any other
573 * As not every engine across every gen support contexts, the returned
574 * value reports the support of context isolation for individual engines by
575 * returning a bitmask of each engine class set to true if that class supports
578 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50
580 /* Frequency of the command streamer timestamps given by the *_TIMESTAMP
581 * registers. This used to be fixed per platform but from CNL onwards, this
582 * might vary depending on the parts.
584 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
587 * Once upon a time we supposed that writes through the GGTT would be
588 * immediately in physical memory (once flushed out of the CPU path). However,
589 * on a few different processors and chipsets, this is not necessarily the case
590 * as the writes appear to be buffered internally. Thus a read of the backing
591 * storage (physical memory) via a different path (with different physical tags
592 * to the indirect write via the GGTT) will see stale values from before
593 * the GGTT write. Inside the kernel, we can for the most part keep track of
594 * the different read/write domains in use (e.g. set-domain), but the assumption
595 * of coherency is baked into the ABI, hence reporting its true state in this
598 * Reports true when writes via mmap_gtt are immediately visible following an
599 * lfence to flush the WCB.
601 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
602 * internal buffer and are _not_ immediately visible to third parties accessing
603 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
604 * communications channel when reporting false is strongly disadvised.
606 #define I915_PARAM_MMAP_GTT_COHERENT 52
609 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
610 * execution through use of explicit fence support.
611 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
613 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
616 * Revision of the i915-perf uAPI. The value returned helps determine what
617 * i915-perf features are available. See drm_i915_perf_property_id.
619 #define I915_PARAM_PERF_REVISION 54
621 /* Must be kept compact -- no holes and well documented */
623 typedef struct drm_i915_getparam
{
626 * WARNING: Using pointers instead of fixed-size u64 means we need to write
627 * compat32 code. Don't repeat this mistake.
630 } drm_i915_getparam_t
;
632 /* Ioctl to set kernel params:
634 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
635 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
636 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
637 #define I915_SETPARAM_NUM_USED_FENCES 4
638 /* Must be kept compact -- no holes */
640 typedef struct drm_i915_setparam
{
643 } drm_i915_setparam_t
;
645 /* A memory manager for regions of shared memory:
647 #define I915_MEM_REGION_AGP 1
649 typedef struct drm_i915_mem_alloc
{
653 int *region_offset
; /* offset from start of fb or agp */
654 } drm_i915_mem_alloc_t
;
656 typedef struct drm_i915_mem_free
{
659 } drm_i915_mem_free_t
;
661 typedef struct drm_i915_mem_init_heap
{
665 } drm_i915_mem_init_heap_t
;
667 /* Allow memory manager to be torn down and re-initialized (eg on
670 typedef struct drm_i915_mem_destroy_heap
{
672 } drm_i915_mem_destroy_heap_t
;
674 /* Allow X server to configure which pipes to monitor for vblank signals
676 #define DRM_I915_VBLANK_PIPE_A 1
677 #define DRM_I915_VBLANK_PIPE_B 2
679 typedef struct drm_i915_vblank_pipe
{
681 } drm_i915_vblank_pipe_t
;
683 /* Schedule buffer swap at given vertical blank:
685 typedef struct drm_i915_vblank_swap
{
686 drm_drawable_t drawable
;
687 enum drm_vblank_seq_type seqtype
;
688 unsigned int sequence
;
689 } drm_i915_vblank_swap_t
;
691 typedef struct drm_i915_hws_addr
{
693 } drm_i915_hws_addr_t
;
695 struct drm_i915_gem_init
{
697 * Beginning offset in the GTT to be managed by the DRM memory
702 * Ending offset in the GTT to be managed by the DRM memory
708 struct drm_i915_gem_create
{
710 * Requested size for the object.
712 * The (page-aligned) allocated size for the object will be returned.
716 * Returned handle for the object.
718 * Object handles are nonzero.
724 struct drm_i915_gem_pread
{
725 /** Handle for the object being read. */
728 /** Offset into the object to read from */
730 /** Length of data to read */
733 * Pointer to write the data into.
735 * This is a fixed-size type for 32/64 compatibility.
740 struct drm_i915_gem_pwrite
{
741 /** Handle for the object being written to. */
744 /** Offset into the object to write to */
746 /** Length of data to write */
749 * Pointer to read the data from.
751 * This is a fixed-size type for 32/64 compatibility.
756 struct drm_i915_gem_mmap
{
757 /** Handle for the object being mapped. */
760 /** Offset in the object to map. */
763 * Length of data to map.
765 * The value will be page-aligned.
769 * Returned pointer the data was mapped at.
771 * This is a fixed-size type for 32/64 compatibility.
776 * Flags for extended behaviour.
778 * Added in version 2.
781 #define I915_MMAP_WC 0x1
784 struct drm_i915_gem_mmap_gtt
{
785 /** Handle for the object being mapped. */
789 * Fake offset to use for subsequent mmap call
791 * This is a fixed-size type for 32/64 compatibility.
796 struct drm_i915_gem_set_domain
{
797 /** Handle for the object */
800 /** New read domains */
803 /** New write domain */
807 struct drm_i915_gem_sw_finish
{
808 /** Handle for the object */
812 struct drm_i915_gem_relocation_entry
{
814 * Handle of the buffer being pointed to by this relocation entry.
816 * It's appealing to make this be an index into the mm_validate_entry
817 * list to refer to the buffer, but this allows the driver to create
818 * a relocation list for state buffers and not re-write it per
819 * exec using the buffer.
824 * Value to be added to the offset of the target buffer to make up
825 * the relocation entry.
829 /** Offset in the buffer the relocation entry will be written into */
833 * Offset value of the target buffer that the relocation entry was last
836 * If the buffer has the same offset as last time, we can skip syncing
837 * and writing the relocation. This value is written back out by
838 * the execbuffer ioctl when the relocation is written.
840 __u64 presumed_offset
;
843 * Target memory domains read by this operation.
848 * Target memory domains written by this operation.
850 * Note that only one domain may be written by the whole
851 * execbuffer operation, so that where there are conflicts,
852 * the application will get -EINVAL back.
858 * Intel memory domains
860 * Most of these just align with the various caches in
861 * the system and are used to flush and invalidate as
862 * objects end up cached in different domains.
865 #define I915_GEM_DOMAIN_CPU 0x00000001
866 /** Render cache, used by 2D and 3D drawing */
867 #define I915_GEM_DOMAIN_RENDER 0x00000002
868 /** Sampler cache, used by texture engine */
869 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
870 /** Command queue, used to load batch buffers */
871 #define I915_GEM_DOMAIN_COMMAND 0x00000008
872 /** Instruction cache, used by shader programs */
873 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
874 /** Vertex address cache */
875 #define I915_GEM_DOMAIN_VERTEX 0x00000020
876 /** GTT domain - aperture and scanout */
877 #define I915_GEM_DOMAIN_GTT 0x00000040
878 /** WC domain - uncached access */
879 #define I915_GEM_DOMAIN_WC 0x00000080
882 struct drm_i915_gem_exec_object
{
884 * User's handle for a buffer to be bound into the GTT for this
889 /** Number of relocations to be performed on this buffer */
890 __u32 relocation_count
;
892 * Pointer to array of struct drm_i915_gem_relocation_entry containing
893 * the relocations to be performed in this buffer.
897 /** Required alignment in graphics aperture */
901 * Returned value of the updated offset of the object, for future
902 * presumed_offset writes.
907 struct drm_i915_gem_execbuffer
{
909 * List of buffers to be validated with their relocations to be
910 * performend on them.
912 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
914 * These buffers must be listed in an order such that all relocations
915 * a buffer is performing refer to buffers that have already appeared
916 * in the validate list.
921 /** Offset in the batchbuffer to start execution from. */
922 __u32 batch_start_offset
;
923 /** Bytes used in batchbuffer from batch_start_offset */
928 /** This is a struct drm_clip_rect *cliprects */
932 struct drm_i915_gem_exec_object2
{
934 * User's handle for a buffer to be bound into the GTT for this
939 /** Number of relocations to be performed on this buffer */
940 __u32 relocation_count
;
942 * Pointer to array of struct drm_i915_gem_relocation_entry containing
943 * the relocations to be performed in this buffer.
947 /** Required alignment in graphics aperture */
951 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
952 * the user with the GTT offset at which this object will be pinned.
953 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
954 * presumed_offset of the object.
955 * During execbuffer2 the kernel populates it with the value of the
956 * current GTT offset of the object, for future presumed_offset writes.
960 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
961 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
962 #define EXEC_OBJECT_WRITE (1<<2)
963 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
964 #define EXEC_OBJECT_PINNED (1<<4)
965 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
966 /* The kernel implicitly tracks GPU activity on all GEM objects, and
967 * synchronises operations with outstanding rendering. This includes
968 * rendering on other devices if exported via dma-buf. However, sometimes
969 * this tracking is too coarse and the user knows better. For example,
970 * if the object is split into non-overlapping ranges shared between different
971 * clients or engines (i.e. suballocating objects), the implicit tracking
972 * by kernel assumes that each operation affects the whole object rather
973 * than an individual range, causing needless synchronisation between clients.
974 * The kernel will also forgo any CPU cache flushes prior to rendering from
975 * the object as the client is expected to be also handling such domain
978 * The kernel maintains the implicit tracking in order to manage resources
979 * used by the GPU - this flag only disables the synchronisation prior to
980 * rendering with this object in this execbuf.
982 * Opting out of implicit synhronisation requires the user to do its own
983 * explicit tracking to avoid rendering corruption. See, for example,
984 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
986 #define EXEC_OBJECT_ASYNC (1<<6)
987 /* Request that the contents of this execobject be copied into the error
988 * state upon a GPU hang involving this batch for post-mortem debugging.
989 * These buffers are recorded in no particular order as "user" in
990 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
991 * if the kernel supports this flag.
993 #define EXEC_OBJECT_CAPTURE (1<<7)
994 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
995 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
1005 struct drm_i915_gem_exec_fence
{
1007 * User's handle for a drm_syncobj to wait on or signal.
1011 #define I915_EXEC_FENCE_WAIT (1<<0)
1012 #define I915_EXEC_FENCE_SIGNAL (1<<1)
1013 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
1017 struct drm_i915_gem_execbuffer2
{
1019 * List of gem_exec_object2 structs
1024 /** Offset in the batchbuffer to start execution from. */
1025 __u32 batch_start_offset
;
1026 /** Bytes used in batchbuffer from batch_start_offset */
1030 __u32 num_cliprects
;
1032 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
1033 * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
1034 * struct drm_i915_gem_exec_fence *fences.
1036 __u64 cliprects_ptr
;
1037 #define I915_EXEC_RING_MASK (0x3f)
1038 #define I915_EXEC_DEFAULT (0<<0)
1039 #define I915_EXEC_RENDER (1<<0)
1040 #define I915_EXEC_BSD (2<<0)
1041 #define I915_EXEC_BLT (3<<0)
1042 #define I915_EXEC_VEBOX (4<<0)
1044 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
1045 * Gen6+ only supports relative addressing to dynamic state (default) and
1046 * absolute addressing.
1048 * These flags are ignored for the BSD and BLT rings.
1050 #define I915_EXEC_CONSTANTS_MASK (3<<6)
1051 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
1052 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
1053 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1055 __u64 rsvd1
; /* now used for context info */
1059 /** Resets the SO write offset registers for transform feedback on gen7. */
1060 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
1062 /** Request a privileged ("secure") batch buffer. Note only available for
1063 * DRM_ROOT_ONLY | DRM_MASTER processes.
1065 #define I915_EXEC_SECURE (1<<9)
1067 /** Inform the kernel that the batch is and will always be pinned. This
1068 * negates the requirement for a workaround to be performed to avoid
1069 * an incoherent CS (such as can be found on 830/845). If this flag is
1070 * not passed, the kernel will endeavour to make sure the batch is
1071 * coherent with the CS before execution. If this flag is passed,
1072 * userspace assumes the responsibility for ensuring the same.
1074 #define I915_EXEC_IS_PINNED (1<<10)
1076 /** Provide a hint to the kernel that the command stream and auxiliary
1077 * state buffers already holds the correct presumed addresses and so the
1078 * relocation process may be skipped if no buffers need to be moved in
1079 * preparation for the execbuffer.
1081 #define I915_EXEC_NO_RELOC (1<<11)
1083 /** Use the reloc.handle as an index into the exec object array rather
1084 * than as the per-file handle.
1086 #define I915_EXEC_HANDLE_LUT (1<<12)
1088 /** Used for switching BSD rings on the platforms with two BSD rings */
1089 #define I915_EXEC_BSD_SHIFT (13)
1090 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1091 /* default ping-pong mode */
1092 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1093 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1094 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1096 /** Tell the kernel that the batchbuffer is processed by
1097 * the resource streamer.
1099 #define I915_EXEC_RESOURCE_STREAMER (1<<15)
1101 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1102 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1105 * Returns -EINVAL if the sync_file fd cannot be found.
1107 #define I915_EXEC_FENCE_IN (1<<16)
1109 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1110 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1111 * to the caller, and it should be close() after use. (The fd is a regular
1112 * file descriptor and will be cleaned up on process termination. It holds
1113 * a reference to the request, but nothing else.)
1115 * The sync_file fd can be combined with other sync_file and passed either
1116 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1117 * will only occur after this request completes), or to other devices.
1119 * Using I915_EXEC_FENCE_OUT requires use of
1120 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1121 * back to userspace. Failure to do so will cause the out-fence to always
1122 * be reported as zero, and the real fence fd to be leaked.
1124 #define I915_EXEC_FENCE_OUT (1<<17)
1127 * Traditionally the execbuf ioctl has only considered the final element in
1128 * the execobject[] to be the executable batch. Often though, the client
1129 * will known the batch object prior to construction and being able to place
1130 * it into the execobject[] array first can simplify the relocation tracking.
1131 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1132 * execobject[] as the * batch instead (the default is to use the last
1135 #define I915_EXEC_BATCH_FIRST (1<<18)
1137 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1138 * define an array of i915_gem_exec_fence structures which specify a set of
1139 * dma fences to wait upon or signal.
1141 #define I915_EXEC_FENCE_ARRAY (1<<19)
1144 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1145 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1148 * Returns -EINVAL if the sync_file fd cannot be found.
1150 #define I915_EXEC_FENCE_SUBMIT (1 << 20)
1152 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
1154 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1155 #define i915_execbuffer2_set_context_id(eb2, context) \
1156 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1157 #define i915_execbuffer2_get_context_id(eb2) \
1158 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1160 struct drm_i915_gem_pin
{
1161 /** Handle of the buffer to be pinned. */
1165 /** alignment required within the aperture */
1168 /** Returned GTT offset of the buffer. */
1172 struct drm_i915_gem_unpin
{
1173 /** Handle of the buffer to be unpinned. */
1178 struct drm_i915_gem_busy
{
1179 /** Handle of the buffer to check for busy */
1182 /** Return busy status
1184 * A return of 0 implies that the object is idle (after
1185 * having flushed any pending activity), and a non-zero return that
1186 * the object is still in-flight on the GPU. (The GPU has not yet
1187 * signaled completion for all pending requests that reference the
1188 * object.) An object is guaranteed to become idle eventually (so
1189 * long as no new GPU commands are executed upon it). Due to the
1190 * asynchronous nature of the hardware, an object reported
1191 * as busy may become idle before the ioctl is completed.
1193 * Furthermore, if the object is busy, which engine is busy is only
1194 * provided as a guide and only indirectly by reporting its class
1195 * (there may be more than one engine in each class). There are race
1196 * conditions which prevent the report of which engines are busy from
1197 * being always accurate. However, the converse is not true. If the
1198 * object is idle, the result of the ioctl, that all engines are idle,
1201 * The returned dword is split into two fields to indicate both
1202 * the engine classess on which the object is being read, and the
1203 * engine class on which it is currently being written (if any).
1205 * The low word (bits 0:15) indicate if the object is being written
1206 * to by any engine (there can only be one, as the GEM implicit
1207 * synchronisation rules force writes to be serialised). Only the
1208 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1209 * 1 not 0 etc) for the last write is reported.
1211 * The high word (bits 16:31) are a bitmask of which engines classes
1212 * are currently reading from the object. Multiple engines may be
1213 * reading from the object simultaneously.
1215 * The value of each engine class is the same as specified in the
1216 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1217 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1218 * reported as active itself. Some hardware may have parallel
1219 * execution engines, e.g. multiple media engines, which are
1220 * mapped to the same class identifier and so are not separately
1221 * reported for busyness.
1224 * Only the boolean result of this query is reliable; that is whether
1225 * the object is idle or busy. The report of which engines are busy
1226 * should be only used as a heuristic.
1234 * GPU access is not coherent with cpu caches. Default for machines without an
1237 #define I915_CACHING_NONE 0
1239 * I915_CACHING_CACHED
1241 * GPU access is coherent with cpu caches and furthermore the data is cached in
1242 * last-level caches shared between cpu cores and the gpu GT. Default on
1243 * machines with HAS_LLC.
1245 #define I915_CACHING_CACHED 1
1247 * I915_CACHING_DISPLAY
1249 * Special GPU caching mode which is coherent with the scanout engines.
1250 * Transparently falls back to I915_CACHING_NONE on platforms where no special
1251 * cache mode (like write-through or gfdt flushing) is available. The kernel
1252 * automatically sets this mode when using a buffer as a scanout target.
1253 * Userspace can manually set this mode to avoid a costly stall and clflush in
1254 * the hotpath of drawing the first frame.
1256 #define I915_CACHING_DISPLAY 2
1258 struct drm_i915_gem_caching
{
1260 * Handle of the buffer to set/get the caching level of. */
1264 * Cacheing level to apply or return value
1266 * bits0-15 are for generic caching control (i.e. the above defined
1267 * values). bits16-31 are reserved for platform-specific variations
1268 * (e.g. l3$ caching on gen7). */
1272 #define I915_TILING_NONE 0
1273 #define I915_TILING_X 1
1274 #define I915_TILING_Y 2
1275 #define I915_TILING_LAST I915_TILING_Y
1277 #define I915_BIT_6_SWIZZLE_NONE 0
1278 #define I915_BIT_6_SWIZZLE_9 1
1279 #define I915_BIT_6_SWIZZLE_9_10 2
1280 #define I915_BIT_6_SWIZZLE_9_11 3
1281 #define I915_BIT_6_SWIZZLE_9_10_11 4
1282 /* Not seen by userland */
1283 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
1284 /* Seen by userland. */
1285 #define I915_BIT_6_SWIZZLE_9_17 6
1286 #define I915_BIT_6_SWIZZLE_9_10_17 7
1288 struct drm_i915_gem_set_tiling
{
1289 /** Handle of the buffer to have its tiling state updated */
1293 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1296 * This value is to be set on request, and will be updated by the
1297 * kernel on successful return with the actual chosen tiling layout.
1299 * The tiling mode may be demoted to I915_TILING_NONE when the system
1300 * has bit 6 swizzling that can't be managed correctly by GEM.
1302 * Buffer contents become undefined when changing tiling_mode.
1307 * Stride in bytes for the object when in I915_TILING_X or
1313 * Returned address bit 6 swizzling required for CPU access through
1319 struct drm_i915_gem_get_tiling
{
1320 /** Handle of the buffer to get tiling state for. */
1324 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1330 * Returned address bit 6 swizzling required for CPU access through
1336 * Returned address bit 6 swizzling required for CPU access through
1337 * mmap mapping whilst bound.
1339 __u32 phys_swizzle_mode
;
1342 struct drm_i915_gem_get_aperture
{
1343 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1347 * Available space in the aperture used by i915_gem_execbuffer, in
1350 __u64 aper_available_size
;
1353 struct drm_i915_get_pipe_from_crtc_id
{
1354 /** ID of CRTC being requested **/
1357 /** pipe of requested CRTC **/
1361 #define I915_MADV_WILLNEED 0
1362 #define I915_MADV_DONTNEED 1
1363 #define __I915_MADV_PURGED 2 /* internal state */
1365 struct drm_i915_gem_madvise
{
1366 /** Handle of the buffer to change the backing store advice */
1369 /* Advice: either the buffer will be needed again in the near future,
1370 * or wont be and could be discarded under memory pressure.
1374 /** Whether the backing store still exists. */
1379 #define I915_OVERLAY_TYPE_MASK 0xff
1380 #define I915_OVERLAY_YUV_PLANAR 0x01
1381 #define I915_OVERLAY_YUV_PACKED 0x02
1382 #define I915_OVERLAY_RGB 0x03
1384 #define I915_OVERLAY_DEPTH_MASK 0xff00
1385 #define I915_OVERLAY_RGB24 0x1000
1386 #define I915_OVERLAY_RGB16 0x2000
1387 #define I915_OVERLAY_RGB15 0x3000
1388 #define I915_OVERLAY_YUV422 0x0100
1389 #define I915_OVERLAY_YUV411 0x0200
1390 #define I915_OVERLAY_YUV420 0x0300
1391 #define I915_OVERLAY_YUV410 0x0400
1393 #define I915_OVERLAY_SWAP_MASK 0xff0000
1394 #define I915_OVERLAY_NO_SWAP 0x000000
1395 #define I915_OVERLAY_UV_SWAP 0x010000
1396 #define I915_OVERLAY_Y_SWAP 0x020000
1397 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1399 #define I915_OVERLAY_FLAGS_MASK 0xff000000
1400 #define I915_OVERLAY_ENABLE 0x01000000
1402 struct drm_intel_overlay_put_image
{
1403 /* various flags and src format description */
1405 /* source picture description */
1407 /* stride values and offsets are in bytes, buffer relative */
1408 __u16 stride_Y
; /* stride for packed formats */
1410 __u32 offset_Y
; /* offset for packet formats */
1416 /* to compensate the scaling factors for partially covered surfaces */
1417 __u16 src_scan_width
;
1418 __u16 src_scan_height
;
1419 /* output crtc description */
1428 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1429 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1430 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1431 struct drm_intel_overlay_attrs
{
1446 * Intel sprite handling
1448 * Color keying works with a min/mask/max tuple. Both source and destination
1449 * color keying is allowed.
1452 * Sprite pixels within the min & max values, masked against the color channels
1453 * specified in the mask field, will be transparent. All other pixels will
1454 * be displayed on top of the primary plane. For RGB surfaces, only the min
1455 * and mask fields will be used; ranged compares are not allowed.
1457 * Destination keying:
1458 * Primary plane pixels that match the min value, masked against the color
1459 * channels specified in the mask field, will be replaced by corresponding
1460 * pixels from the sprite plane.
1462 * Note that source & destination keying are exclusive; only one can be
1463 * active on a given plane.
1466 #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1467 * flags==0 to disable colorkeying.
1469 #define I915_SET_COLORKEY_DESTINATION (1<<1)
1470 #define I915_SET_COLORKEY_SOURCE (1<<2)
1471 struct drm_intel_sprite_colorkey
{
1479 struct drm_i915_gem_wait
{
1480 /** Handle of BO we shall wait on */
1483 /** Number of nanoseconds to wait, Returns time remaining. */
1487 struct drm_i915_gem_context_create
{
1488 __u32 ctx_id
; /* output: id of new context*/
1492 struct drm_i915_gem_context_create_ext
{
1493 __u32 ctx_id
; /* output: id of new context*/
1495 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1496 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1497 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1498 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1502 struct drm_i915_gem_context_param
{
1506 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1507 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1508 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1509 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1510 #define I915_CONTEXT_PARAM_BANNABLE 0x5
1511 #define I915_CONTEXT_PARAM_PRIORITY 0x6
1512 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1513 #define I915_CONTEXT_DEFAULT_PRIORITY 0
1514 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1516 * When using the following param, value should be a pointer to
1517 * drm_i915_gem_context_param_sseu.
1519 #define I915_CONTEXT_PARAM_SSEU 0x7
1522 * Not all clients may want to attempt automatic recover of a context after
1523 * a hang (for example, some clients may only submit very small incremental
1524 * batches relying on known logical state of previous batches which will never
1525 * recover correctly and each attempt will hang), and so would prefer that
1526 * the context is forever banned instead.
1528 * If set to false (0), after a reset, subsequent (and in flight) rendering
1529 * from this context is discarded, and the client will need to create a new
1530 * context to use instead.
1532 * If set to true (1), the kernel will automatically attempt to recover the
1533 * context by skipping the hanging batch and executing the next batch starting
1534 * from the default context state (discarding the incomplete logical context
1535 * state lost due to the reset).
1537 * On creation, all new contexts are marked as recoverable.
1539 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1542 * The id of the associated virtual memory address space (ppGTT) of
1543 * this context. Can be retrieved and passed to another context
1544 * (on the same fd) for both to use the same ppGTT and so share
1545 * address layouts, and avoid reloading the page tables on context
1546 * switches between themselves.
1548 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1550 #define I915_CONTEXT_PARAM_VM 0x9
1553 * I915_CONTEXT_PARAM_ENGINES:
1555 * Bind this context to operate on this subset of available engines. Henceforth,
1556 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1557 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1558 * and upwards. Slots 0...N are filled in using the specified (class, instance).
1560 * engine_class: I915_ENGINE_CLASS_INVALID,
1561 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1562 * to specify a gap in the array that can be filled in later, e.g. by a
1563 * virtual engine used for load balancing.
1565 * Setting the number of engines bound to the context to 0, by passing a zero
1566 * sized argument, will revert back to default settings.
1568 * See struct i915_context_param_engines.
1571 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1572 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1574 #define I915_CONTEXT_PARAM_ENGINES 0xa
1575 /* Must be kept compact -- no holes and well documented */
1581 * Context SSEU programming
1583 * It may be necessary for either functional or performance reason to configure
1584 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1587 * This is done by configuring SSEU configuration using the below
1588 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1589 * userspace intends to use.
1591 * Not all GPUs or engines support this functionality in which case an error
1592 * code -ENODEV will be returned.
1594 * Also, flexibility of possible SSEU configuration permutations varies between
1595 * GPU generations and software imposed limitations. Requesting such a
1596 * combination will return an error code of -EINVAL.
1598 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1599 * favour of a single global setting.
1601 struct drm_i915_gem_context_param_sseu
{
1603 * Engine class & instance to be configured or queried.
1605 struct i915_engine_class_instance engine
;
1608 * Unknown flags must be cleared to zero.
1611 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
1614 * Mask of slices to enable for the context. Valid values are a subset
1615 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1620 * Mask of subslices to enable for the context. Valid values are a
1621 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1623 __u64 subslice_mask
;
1626 * Minimum/Maximum number of EUs to enable per subslice for the
1627 * context. min_eus_per_subslice must be inferior or equal to
1628 * max_eus_per_subslice.
1630 __u16 min_eus_per_subslice
;
1631 __u16 max_eus_per_subslice
;
1634 * Unused for now. Must be cleared to zero.
1640 * i915_context_engines_load_balance:
1642 * Enable load balancing across this set of engines.
1644 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1645 * used will proxy the execbuffer request onto one of the set of engines
1646 * in such a way as to distribute the load evenly across the set.
1648 * The set of engines must be compatible (e.g. the same HW class) as they
1649 * will share the same logical GPU context and ring.
1651 * To intermix rendering with the virtual engine and direct rendering onto
1652 * the backing engines (bypassing the load balancing proxy), the context must
1653 * be defined to use a single timeline for all engines.
1655 struct i915_context_engines_load_balance
{
1656 struct i915_user_extension base
;
1660 __u32 flags
; /* all undefined flags must be zero */
1662 __u64 mbz64
; /* reserved for future use; must be zero */
1664 struct i915_engine_class_instance engines
[0];
1665 } __attribute__((packed
));
1667 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
1668 struct i915_user_extension base; \
1669 __u16 engine_index; \
1670 __u16 num_siblings; \
1673 struct i915_engine_class_instance engines[N__]; \
1674 } __attribute__((packed)) name__
1677 * i915_context_engines_bond:
1679 * Constructed bonded pairs for execution within a virtual engine.
1681 * All engines are equal, but some are more equal than others. Given
1682 * the distribution of resources in the HW, it may be preferable to run
1683 * a request on a given subset of engines in parallel to a request on a
1684 * specific engine. We enable this selection of engines within a virtual
1685 * engine by specifying bonding pairs, for any given master engine we will
1686 * only execute on one of the corresponding siblings within the virtual engine.
1688 * To execute a request in parallel on the master engine and a sibling requires
1689 * coordination with a I915_EXEC_FENCE_SUBMIT.
1691 struct i915_context_engines_bond
{
1692 struct i915_user_extension base
;
1694 struct i915_engine_class_instance master
;
1696 __u16 virtual_index
; /* index of virtual engine in ctx->engines[] */
1699 __u64 flags
; /* all undefined flags must be zero */
1700 __u64 mbz64
[4]; /* reserved for future use; must be zero */
1702 struct i915_engine_class_instance engines
[0];
1703 } __attribute__((packed
));
1705 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
1706 struct i915_user_extension base; \
1707 struct i915_engine_class_instance master; \
1708 __u16 virtual_index; \
1712 struct i915_engine_class_instance engines[N__]; \
1713 } __attribute__((packed)) name__
1715 struct i915_context_param_engines
{
1716 __u64 extensions
; /* linked chain of extension blocks, 0 terminates */
1717 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
1718 #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
1719 struct i915_engine_class_instance engines
[0];
1720 } __attribute__((packed
));
1722 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
1724 struct i915_engine_class_instance engines[N__]; \
1725 } __attribute__((packed)) name__
1727 struct drm_i915_gem_context_create_ext_setparam
{
1728 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1729 struct i915_user_extension base
;
1730 struct drm_i915_gem_context_param param
;
1733 struct drm_i915_gem_context_create_ext_clone
{
1734 #define I915_CONTEXT_CREATE_EXT_CLONE 1
1735 struct i915_user_extension base
;
1738 #define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1739 #define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1740 #define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1741 #define I915_CONTEXT_CLONE_SSEU (1u << 3)
1742 #define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1743 #define I915_CONTEXT_CLONE_VM (1u << 5)
1744 #define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1748 struct drm_i915_gem_context_destroy
{
1754 * DRM_I915_GEM_VM_CREATE -
1756 * Create a new virtual memory address space (ppGTT) for use within a context
1757 * on the same file. Extensions can be provided to configure exactly how the
1758 * address space is setup upon creation.
1760 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
1761 * returned in the outparam @id.
1763 * No flags are defined, with all bits reserved and must be zero.
1765 * An extension chain maybe provided, starting with @extensions, and terminated
1766 * by the @next_extension being 0. Currently, no extensions are defined.
1768 * DRM_I915_GEM_VM_DESTROY -
1770 * Destroys a previously created VM id, specified in @id.
1772 * No extensions or flags are allowed currently, and so must be zero.
1774 struct drm_i915_gem_vm_control
{
1780 struct drm_i915_reg_read
{
1783 * For 64bit wide registers where the upper 32bits don't immediately
1784 * follow the lower 32bits, the offset of the lower 32bits must
1788 #define I915_REG_READ_8B_WA (1ul << 0)
1790 __u64 val
; /* Return value */
1795 * Render engine timestamp - 0x2358 + 64bit - gen7+
1796 * - Note this register returns an invalid value if using the default
1797 * single instruction 8byte read, in order to workaround that pass
1798 * flag I915_REG_READ_8B_WA in offset field.
1802 struct drm_i915_reset_stats
{
1806 /* All resets since boot/module reload, for all contexts */
1809 /* Number of batches lost when active in GPU, for this context */
1812 /* Number of batches lost pending for execution, for this context */
1813 __u32 batch_pending
;
1818 struct drm_i915_gem_userptr
{
1822 #define I915_USERPTR_READ_ONLY 0x1
1823 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1825 * Returned handle for the object.
1827 * Object handles are nonzero.
1832 enum drm_i915_oa_format
{
1833 I915_OA_FORMAT_A13
= 1, /* HSW only */
1834 I915_OA_FORMAT_A29
, /* HSW only */
1835 I915_OA_FORMAT_A13_B8_C8
, /* HSW only */
1836 I915_OA_FORMAT_B4_C8
, /* HSW only */
1837 I915_OA_FORMAT_A45_B8_C8
, /* HSW only */
1838 I915_OA_FORMAT_B4_C8_A16
, /* HSW only */
1839 I915_OA_FORMAT_C4_B8
, /* HSW+ */
1843 I915_OA_FORMAT_A12_B8_C8
,
1844 I915_OA_FORMAT_A32u40_A4u32_B8_C8
,
1846 I915_OA_FORMAT_MAX
/* non-ABI */
1849 enum drm_i915_perf_property_id
{
1851 * Open the stream for a specific context handle (as used with
1852 * execbuffer2). A stream opened for a specific context this way
1853 * won't typically require root privileges.
1855 * This property is available in perf revision 1.
1857 DRM_I915_PERF_PROP_CTX_HANDLE
= 1,
1860 * A value of 1 requests the inclusion of raw OA unit reports as
1861 * part of stream samples.
1863 * This property is available in perf revision 1.
1865 DRM_I915_PERF_PROP_SAMPLE_OA
,
1868 * The value specifies which set of OA unit metrics should be
1869 * be configured, defining the contents of any OA unit reports.
1871 * This property is available in perf revision 1.
1873 DRM_I915_PERF_PROP_OA_METRICS_SET
,
1876 * The value specifies the size and layout of OA unit reports.
1878 * This property is available in perf revision 1.
1880 DRM_I915_PERF_PROP_OA_FORMAT
,
1883 * Specifying this property implicitly requests periodic OA unit
1884 * sampling and (at least on Haswell) the sampling frequency is derived
1885 * from this exponent as follows:
1887 * 80ns * 2^(period_exponent + 1)
1889 * This property is available in perf revision 1.
1891 DRM_I915_PERF_PROP_OA_EXPONENT
,
1894 * Specifying this property is only valid when specify a context to
1895 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
1896 * will hold preemption of the particular context we want to gather
1897 * performance data about. The execbuf2 submissions must include a
1898 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
1900 * This property is available in perf revision 3.
1902 DRM_I915_PERF_PROP_HOLD_PREEMPTION
,
1904 DRM_I915_PERF_PROP_MAX
/* non-ABI */
1907 struct drm_i915_perf_open_param
{
1909 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
1910 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
1911 #define I915_PERF_FLAG_DISABLED (1<<2)
1913 /** The number of u64 (id, value) pairs */
1914 __u32 num_properties
;
1917 * Pointer to array of u64 (id, value) pairs configuring the stream
1920 __u64 properties_ptr
;
1924 * Enable data capture for a stream that was either opened in a disabled state
1925 * via I915_PERF_FLAG_DISABLED or was later disabled via
1926 * I915_PERF_IOCTL_DISABLE.
1928 * It is intended to be cheaper to disable and enable a stream than it may be
1929 * to close and re-open a stream with the same configuration.
1931 * It's undefined whether any pending data for the stream will be lost.
1933 * This ioctl is available in perf revision 1.
1935 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1938 * Disable data capture for a stream.
1940 * It is an error to try and read a stream that is disabled.
1942 * This ioctl is available in perf revision 1.
1944 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1947 * Change metrics_set captured by a stream.
1949 * If the stream is bound to a specific context, the configuration change
1950 * will performed __inline__ with that context such that it takes effect before
1951 * the next execbuf submission.
1953 * Returns the previously bound metrics set id, or a negative error code.
1955 * This ioctl is available in perf revision 2.
1957 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
1960 * Common to all i915 perf records
1962 struct drm_i915_perf_record_header
{
1968 enum drm_i915_perf_record_type
{
1971 * Samples are the work horse record type whose contents are extensible
1972 * and defined when opening an i915 perf stream based on the given
1975 * Boolean properties following the naming convention
1976 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
1979 * The order of these sample properties given by userspace has no
1980 * affect on the ordering of data within a sample. The order is
1984 * struct drm_i915_perf_record_header header;
1986 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
1989 DRM_I915_PERF_RECORD_SAMPLE
= 1,
1992 * Indicates that one or more OA reports were not written by the
1993 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
1994 * command collides with periodic sampling - which would be more likely
1995 * at higher sampling frequencies.
1997 DRM_I915_PERF_RECORD_OA_REPORT_LOST
= 2,
2000 * An error occurred that resulted in all pending OA reports being lost.
2002 DRM_I915_PERF_RECORD_OA_BUFFER_LOST
= 3,
2004 DRM_I915_PERF_RECORD_MAX
/* non-ABI */
2008 * Structure to upload perf dynamic configuration into the kernel.
2010 struct drm_i915_perf_oa_config
{
2011 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
2015 __u32 n_boolean_regs
;
2019 * These fields are pointers to tuples of u32 values (register address,
2020 * value). For example the expected length of the buffer pointed by
2021 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
2024 __u64 boolean_regs_ptr
;
2025 __u64 flex_regs_ptr
;
2028 struct drm_i915_query_item
{
2030 #define DRM_I915_QUERY_TOPOLOGY_INFO 1
2031 #define DRM_I915_QUERY_ENGINE_INFO 2
2032 #define DRM_I915_QUERY_PERF_CONFIG 3
2033 /* Must be kept compact -- no holes and well documented */
2036 * When set to zero by userspace, this is filled with the size of the
2037 * data to be written at the data_ptr pointer. The kernel sets this
2038 * value to a negative value to signal an error on a particular query
2044 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
2046 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
2048 * - DRM_I915_QUERY_PERF_CONFIG_LIST
2049 * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
2050 * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
2053 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
2054 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
2055 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
2058 * Data will be written at the location pointed by data_ptr when the
2059 * value of length matches the length of the data to be written by the
2065 struct drm_i915_query
{
2069 * Unused for now. Must be cleared to zero.
2074 * This points to an array of num_items drm_i915_query_item structures.
2080 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
2082 * data: contains the 3 pieces of information :
2084 * - the slice mask with one bit per slice telling whether a slice is
2085 * available. The availability of slice X can be queried with the following
2088 * (data[X / 8] >> (X % 8)) & 1
2090 * - the subslice mask for each slice with one bit per subslice telling
2091 * whether a subslice is available. Gen12 has dual-subslices, which are
2092 * similar to two gen11 subslices. For gen12, this array represents dual-
2093 * subslices. The availability of subslice Y in slice X can be queried
2094 * with the following formula :
2096 * (data[subslice_offset +
2097 * X * subslice_stride +
2098 * Y / 8] >> (Y % 8)) & 1
2100 * - the EU mask for each subslice in each slice with one bit per EU telling
2101 * whether an EU is available. The availability of EU Z in subslice Y in
2102 * slice X can be queried with the following formula :
2105 * (X * max_subslices + Y) * eu_stride +
2106 * Z / 8] >> (Z % 8)) & 1
2108 struct drm_i915_query_topology_info
{
2110 * Unused for now. Must be cleared to zero.
2115 __u16 max_subslices
;
2116 __u16 max_eus_per_subslice
;
2119 * Offset in data[] at which the subslice masks are stored.
2121 __u16 subslice_offset
;
2124 * Stride at which each of the subslice masks for each slice are
2127 __u16 subslice_stride
;
2130 * Offset in data[] at which the EU masks are stored.
2135 * Stride at which each of the EU masks for each subslice are stored.
2143 * struct drm_i915_engine_info
2145 * Describes one engine and it's capabilities as known to the driver.
2147 struct drm_i915_engine_info
{
2148 /** Engine class and instance. */
2149 struct i915_engine_class_instance engine
;
2151 /** Reserved field. */
2154 /** Engine flags. */
2157 /** Capabilities of this engine. */
2159 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2160 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2162 /** Reserved fields. */
2167 * struct drm_i915_query_engine_info
2169 * Engine info query enumerates all engines known to the driver by filling in
2170 * an array of struct drm_i915_engine_info structures.
2172 struct drm_i915_query_engine_info
{
2173 /** Number of struct drm_i915_engine_info structs following. */
2179 /** Marker for drm_i915_engine_info structures. */
2180 struct drm_i915_engine_info engines
[];
2184 * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
2186 struct drm_i915_query_perf_config
{
2189 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
2190 * this fields to the number of configurations available.
2195 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
2196 * i915 will use the value in this field as configuration
2197 * identifier to decide what data to write into config_ptr.
2202 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
2203 * i915 will use the value in this field as configuration
2204 * identifier to decide what data to write into config_ptr.
2206 * String formatted like "%08x-%04x-%04x-%04x-%012x"
2212 * Unused for now. Must be cleared to zero.
2217 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
2218 * write an array of __u64 of configuration identifiers.
2220 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
2221 * write a struct drm_i915_perf_oa_config. If the following fields of
2222 * drm_i915_perf_oa_config are set not set to 0, i915 will write into
2223 * the associated pointers the values of submitted when the
2224 * configuration was created :
2233 #if defined(__cplusplus)
2237 #endif /* _I915_DRM_H_ */