include/opcode/ChangeLog

   1 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   2
   3         * hppa.h (pa_opcodes): Remove lha entries.
   4
   5 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   6
   7         * hppa.h (FLAG_STRICT): Revise comment.
   8         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
   9         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
  10         entries for "fdc".
  11
  12 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  13
  14         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
  15
  16 2005-09-06  Chao-ying Fu  <fu@mips.com>
  17
  18         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
  19         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
  20         define.
  21         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
  22         (INSN_ASE_MASK): Update to include INSN_MT.
  23         (INSN_MT): New define for MT ASE.
  24
  25 2005-08-25  Chao-ying Fu  <fu@mips.com>
  26
  27         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
  28         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
  29         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
  30         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
  31         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
  32         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
  33         instructions.
  34         (INSN_DSP): New define for DSP ASE.
  35
  36 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
  37
  38         * a29k.h: Delete.
  39
  40 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
  41
  42         * ppc.h (PPC_OPCODE_E300): Define.
  43
  44 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
  45
  46         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
  47
  48 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  49
  50         PR gas/336
  51         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
  52         and pitlb.
  53
  54 2005-07-27  Jan Beulich  <jbeulich@novell.com>
  55
  56         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
  57         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
  58         Add movq-s as 64-bit variants of movd-s.
  59
  60 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  61
  62         * hppa.h: Fix punctuation in comment.
  63
  64         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
  65         implicit space-register addressing.  Set space-register bits on opcodes
  66         using implicit space-register addressing.  Add various missing pa20
  67         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
  68         space-register addressing.  Use "fE" instead of "fe" in various
  69         fstw opcodes.
  70
  71 2005-07-18  Jan Beulich  <jbeulich@novell.com>
  72
  73         * i386.h (i386_optab): Operands of aam and aad are unsigned.
  74
  75 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
  76
  77         * i386.h (i386_optab): Support Intel VMX Instructions.
  78
  79 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  80
  81         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
  82
  83 2005-07-05  Jan Beulich  <jbeulich@novell.com>
  84
  85         * i386.h (i386_optab): Add new insns.
  86
  87 2005-07-01  Nick Clifton  <nickc@redhat.com>
  88
  89         * sparc.h: Add typedefs to structure declarations.
  90
  91 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         PR 1013
  94         * i386.h (i386_optab): Update comments for 64bit addressing on
  95         mov. Allow 64bit addressing for mov and movq.
  96
  97 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  98
  99         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 100         respectively, in various floating-point load and store patterns.
 101
 102 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 103
 104         * hppa.h (FLAG_STRICT): Correct comment.
 105         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 106         PA 2.0 mneumonics when equivalent.  Entries with cache control
 107         completers now require PA 1.1.  Adjust whitespace.
 108
 109 2005-05-19  Anton Blanchard  <anton@samba.org>
 110
 111         * ppc.h (PPC_OPCODE_POWER5): Define.
 112
 113 2005-05-10  Nick Clifton  <nickc@redhat.com>
 114
 115         * Update the address and phone number of the FSF organization in
 116         the GPL notices in the following files:
 117         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 118         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 119         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 120         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 121         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 122         tic54x.h, tic80.h, v850.h, vax.h
 123
 124 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 125
 126         * i386.h (i386_optab): Add ht and hnt.
 127
 128 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 129
 130         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 131         Add xcrypt-ctr.  Provide aliases without hyphens.
 132
 133 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 134
 135         Moved from ../ChangeLog
 136
 137         2005-04-12  Paul Brook  <paul@codesourcery.com>
 138         * m88k.h: Rename psr macros to avoid conflicts.
 139
 140         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 141         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 142         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 143         and ARM_ARCH_V6ZKT2.
 144
 145         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 146         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 147         Remove redundant instruction types.
 148         (struct argument): X_op - new field.
 149         (struct cst4_entry): Remove.
 150         (no_op_insn): Declare.
 151
 152         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 153         * crx.h (enum argtype): Rename types, remove unused types.
 154
 155         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 156         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 157         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 158         (enum operand_type): Rearrange operands, edit comments.
 159         replace us<N> with ui<N> for unsigned immediate.
 160         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 161         displacements (respectively).
 162         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 163         (instruction type): Add NO_TYPE_INS.
 164         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 165         (operand_entry): New field - 'flags'.
 166         (operand flags): New.
 167
 168         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 169         * crx.h (operand_type): Remove redundant types i3, i4,
 170         i5, i8, i12.
 171         Add new unsigned immediate types us3, us4, us5, us16.
 172
 173 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 174
 175         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 176         adjust them accordingly.
 177
 178 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 179
 180         * i386.h (i386_optab): Add rdtscp.
 181
 182 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 185         between memory and segment register. Allow movq for moving between
 186         general-purpose register and segment register.
 187
 188 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 189
 190         PR gas/707
 191         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 192         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 193         fnstsw.
 194
 195 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 196
 197         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 198         * cgen.h (enum cgen_parse_operand_type): Add
 199         CGEN_PARSE_OPERAND_SYMBOLIC.
 200
 201 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 202
 203         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 204         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 205         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 206
 207 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 208
 209         * mips.h (struct mips_opcode): Add new pinfo2 member.
 210         (INSN_ALIAS): New define for opcode table entries that are
 211         specific instances of another entry, such as 'move' for an 'or'
 212         with a zero operand.
 213         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 214         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 215
 216 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 217
 218         * mips.h (CPU_RM9000): Define.
 219         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 220
 221 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 222
 223         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 224         to/from test registers are illegal in 64-bit mode. Add missing
 225         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 226         (previously one had to explicitly encode a rex64 prefix). Re-enable
 227         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 228         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 229
 230 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 231
 232         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 233         available only with SSE2. Change the MMX additions introduced by SSE
 234         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 235         instructions by their now designated identifier (since combining i686
 236         and 3DNow! does not really imply 3DNow!A).
 237
 238 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 239
 240         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 241         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 242
 243 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 244             Vineet Sharma      <vineets@noida.hcltech.com>
 245
 246         * maxq.h: New file: Disassembly information for the maxq port.
 247
 248 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 249
 250         * i386.h (i386_optab): Put back "movzb".
 251
 252 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 253
 254         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 255         comments.  Remove member cris_ver_sim.  Add members
 256         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 257         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 258         (struct cris_support_reg, struct cris_cond15): New types.
 259         (cris_conds15): Declare.
 260         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 261         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 262         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 263         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 264         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 265         SIZE_FIELD_UNSIGNED.
 266
 267 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 268
 269         * i386.h (sldx_Suf): Remove.
 270         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 271         (q_FP): Define, implying no REX64.
 272         (x_FP, sl_FP): Imply FloatMF.
 273         (i386_optab): Split reg and mem forms of moving from segment registers
 274         so that the memory forms can ignore the 16-/32-bit operand size
 275         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 276         all non-floating-point instructions. Unite 32- and 64-bit forms of
 277         movsx, movzx, and movd. Adjust floating point operations for the above
 278         changes to the *FP macros. Add DefaultSize to floating point control
 279         insns operating on larger memory ranges. Remove left over comments
 280         hinting at certain insns being Intel-syntax ones where the ones
 281         actually meant are already gone.
 282
 283 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 284
 285         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 286         instruction type.
 287
 288 2004-09-30  Paul Brook  <paul@codesourcery.com>
 289
 290         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 291         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 292
 293 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 294
 295         * avr.h: Add support for
 296         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 297
 298 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 299
 300         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 301
 302 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 303
 304         * msp430.h (msp430_opc): Add new instructions.
 305         (msp430_rcodes): Declare new instructions.
 306         (msp430_hcodes): Likewise..
 307
 308 2004-08-13  Nick Clifton  <nickc@redhat.com>
 309
 310         PR/301
 311         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 312         processors.
 313
 314 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 315
 316         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 317
 318 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 321
 322 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 323
 324         * i386.h: Adjust instruction descriptions to better match the
 325         specification.
 326
 327 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 328
 329         * arm.h: Remove all old content.  Replace with architecture defines
 330         from gas/config/tc-arm.c.
 331
 332 2004-07-09  Andreas Schwab  <schwab@suse.de>
 333
 334         * m68k.h: Fix comment.
 335
 336 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 337
 338         * crx.h: New file.
 339
 340 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 341
 342         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 343
 344 2004-05-24  Peter Barada  <peter@the-baradas.com>
 345
 346         * m68k.h: Add 'size' to m68k_opcode.
 347
 348 2004-05-05  Peter Barada  <peter@the-baradas.com>
 349
 350         * m68k.h: Switch from ColdFire chip name to core variant.
 351
 352 2004-04-22  Peter Barada  <peter@the-baradas.com>
 353
 354         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 355         descriptions for new EMAC cases.
 356         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 357         handle Motorola MAC syntax.
 358         Allow disassembly of ColdFire V4e object files.
 359
 360 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 361
 362         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 363
 364 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 365
 366         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 367
 368 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 369
 370         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 371
 372 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 373
 374         * i386.h (i386_optab): Added xstore/xcrypt insns.
 375
 376 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 377
 378         * h8300.h (32bit ldc/stc): Add relaxing support.
 379
 380 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 381
 382         * h8300.h (BITOP): Pass MEMRELAX flag.
 383
 384 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 385
 386         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 387         except for the H8S.
 388
 389 For older changes see ChangeLog-9103
 390 \f
 391 Local Variables:
 392 mode: change-log
 393 left-margin: 8
 394 fill-column: 74
 395 version-control: never
 396 End: