include/opcode/ChangeLog

   1 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386.h: Replace CpuMNI with CpuSSSE3.
   4
   5 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
   6             Joseph Myers  <joseph@codesourcery.com>
   7             Ian Lance Taylor  <ian@wasabisystems.com>
   8             Ben Elliston  <bje@wasabisystems.com>
   9
  10         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  11
  12 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  13
  14         * score-datadep.h: New file.
  15         * score-inst.h: New file.
  16
  17 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  20         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  21         movdq2q and movq2dq.
  22
  23 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  24            Michael Meissner             <michael.meissner@amd.com>
  25
  26         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  27
  28 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         * i386.h (i386_optab): Add "nop" with memory reference.
  31
  32 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  33
  34         * i386.h (i386_optab): Update comment for 64bit NOP.
  35
  36 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  37             Anton Blanchard  <anton@samba.org>
  38
  39         * ppc.h (PPC_OPCODE_POWER6): Define.
  40         Adjust whitespace.
  41
  42 2006-06-05  Thiemo Seufer  <ths@mips.com>
  43
  44         * mips.h: Improve description of MT flags.
  45
  46 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  47
  48         * m68k.h (mcf_mask): Define.
  49
  50 2006-05-05  Thiemo Seufer  <ths@mips.com>
  51             David Ung  <davidu@mips.com>
  52
  53         * mips.h (enum): Add macro M_CACHE_AB.
  54
  55 2006-05-04  Thiemo Seufer  <ths@mips.com>
  56             Nigel Stephens  <nigel@mips.com>
  57             David Ung  <davidu@mips.com>
  58
  59         * mips.h: Add INSN_SMARTMIPS define.
  60
  61 2006-04-30  Thiemo Seufer  <ths@mips.com>
  62             David Ung  <davidu@mips.com>
  63
  64         * mips.h: Defines udi bits and masks.  Add description of
  65         characters which may appear in the args field of udi
  66         instructions.
  67
  68 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  69
  70         * mips.h: Improve comments describing the bitfield instruction
  71         fields.
  72
  73 2006-04-26  Julian Brown  <julian@codesourcery.com>
  74
  75         * arm.h (FPU_VFP_EXT_V3): Define constant.
  76         (FPU_NEON_EXT_V1): Likewise.
  77         (FPU_VFP_HARD): Update.
  78         (FPU_VFP_V3): Define macro.
  79         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
  80
  81 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
  82
  83         * avr.h (AVR_ISA_PWMx): New.
  84
  85 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
  86
  87         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
  88         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
  89         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
  90         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
  91         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
  92
  93 2006-03-10  Paul Brook  <paul@codesourcery.com>
  94
  95         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
  96
  97 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  98
  99         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 100         first.  Correct mask of bb "B" opcode.
 101
 102 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 103
 104         * i386.h (i386_optab): Support Intel Merom New Instructions.
 105
 106 2006-02-24  Paul Brook  <paul@codesourcery.com>
 107
 108         * arm.h: Add V7 feature bits.
 109
 110 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 111
 112         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 113
 114 2006-01-31  Paul Brook  <paul@codesourcery.com>
 115         Richard Earnshaw <rearnsha@arm.com>
 116
 117         * arm.h: Use ARM_CPU_FEATURE.
 118         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 119         (arm_feature_set): Change to a structure.
 120         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 121         ARM_FEATURE): New macros.
 122
 123 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 124
 125         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 126         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 127         (ADD_PC_INCR_OPCODE): Don't define.
 128
 129 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         PR gas/1874
 132         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 133
 134 2005-11-14  David Ung  <davidu@mips.com>
 135
 136         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 137         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 138         save/restore encoding of the args field.
 139
 140 2005-10-28  Dave Brolley  <brolley@redhat.com>
 141
 142         Contribute the following changes:
 143         2005-02-16  Dave Brolley  <brolley@redhat.com>
 144
 145         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 146         cgen_isa_mask_* to cgen_bitset_*.
 147         * cgen.h: Likewise.
 148
 149         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 150
 151         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 152         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 153         (CGEN_CPU_TABLE): Make isas a ponter.
 154
 155         2003-09-29  Dave Brolley  <brolley@redhat.com>
 156
 157         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 158         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 159         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 160
 161         2002-12-13  Dave Brolley  <brolley@redhat.com>
 162
 163         * cgen.h (symcat.h): #include it.
 164         (cgen-bitset.h): #include it.
 165         (CGEN_ATTR_VALUE_TYPE): Now a union.
 166         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 167         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 168         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 169         * cgen-bitset.h: New file.
 170
 171 2005-09-30  Catherine Moore  <clm@cm00re.com>
 172
 173         * bfin.h: New file.
 174
 175 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 176
 177         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 178         indirect operands.
 179
 180 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 181
 182         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 183         Add FLAG_STRICT to pa10 ftest opcode.
 184
 185 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 186
 187         * hppa.h (pa_opcodes): Remove lha entries.
 188
 189 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 190
 191         * hppa.h (FLAG_STRICT): Revise comment.
 192         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 193         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 194         entries for "fdc".
 195
 196 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 197
 198         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 199
 200 2005-09-06  Chao-ying Fu  <fu@mips.com>
 201
 202         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 203         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 204         define.
 205         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 206         (INSN_ASE_MASK): Update to include INSN_MT.
 207         (INSN_MT): New define for MT ASE.
 208
 209 2005-08-25  Chao-ying Fu  <fu@mips.com>
 210
 211         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 212         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 213         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 214         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 215         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 216         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 217         instructions.
 218         (INSN_DSP): New define for DSP ASE.
 219
 220 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 221
 222         * a29k.h: Delete.
 223
 224 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 225
 226         * ppc.h (PPC_OPCODE_E300): Define.
 227
 228 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 229
 230         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 231
 232 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 233
 234         PR gas/336
 235         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 236         and pitlb.
 237
 238 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 239
 240         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 241         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 242         Add movq-s as 64-bit variants of movd-s.
 243
 244 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 245
 246         * hppa.h: Fix punctuation in comment.
 247
 248         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 249         implicit space-register addressing.  Set space-register bits on opcodes
 250         using implicit space-register addressing.  Add various missing pa20
 251         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 252         space-register addressing.  Use "fE" instead of "fe" in various
 253         fstw opcodes.
 254
 255 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 256
 257         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 258
 259 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 260
 261         * i386.h (i386_optab): Support Intel VMX Instructions.
 262
 263 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 264
 265         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 266
 267 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 268
 269         * i386.h (i386_optab): Add new insns.
 270
 271 2005-07-01  Nick Clifton  <nickc@redhat.com>
 272
 273         * sparc.h: Add typedefs to structure declarations.
 274
 275 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 276
 277         PR 1013
 278         * i386.h (i386_optab): Update comments for 64bit addressing on
 279         mov. Allow 64bit addressing for mov and movq.
 280
 281 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 282
 283         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 284         respectively, in various floating-point load and store patterns.
 285
 286 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 287
 288         * hppa.h (FLAG_STRICT): Correct comment.
 289         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 290         PA 2.0 mneumonics when equivalent.  Entries with cache control
 291         completers now require PA 1.1.  Adjust whitespace.
 292
 293 2005-05-19  Anton Blanchard  <anton@samba.org>
 294
 295         * ppc.h (PPC_OPCODE_POWER5): Define.
 296
 297 2005-05-10  Nick Clifton  <nickc@redhat.com>
 298
 299         * Update the address and phone number of the FSF organization in
 300         the GPL notices in the following files:
 301         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 302         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 303         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 304         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 305         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 306         tic54x.h, tic80.h, v850.h, vax.h
 307
 308 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 309
 310         * i386.h (i386_optab): Add ht and hnt.
 311
 312 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 313
 314         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 315         Add xcrypt-ctr.  Provide aliases without hyphens.
 316
 317 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         Moved from ../ChangeLog
 320
 321         2005-04-12  Paul Brook  <paul@codesourcery.com>
 322         * m88k.h: Rename psr macros to avoid conflicts.
 323
 324         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 325         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 326         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 327         and ARM_ARCH_V6ZKT2.
 328
 329         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 330         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 331         Remove redundant instruction types.
 332         (struct argument): X_op - new field.
 333         (struct cst4_entry): Remove.
 334         (no_op_insn): Declare.
 335
 336         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 337         * crx.h (enum argtype): Rename types, remove unused types.
 338
 339         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 340         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 341         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 342         (enum operand_type): Rearrange operands, edit comments.
 343         replace us<N> with ui<N> for unsigned immediate.
 344         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 345         displacements (respectively).
 346         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 347         (instruction type): Add NO_TYPE_INS.
 348         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 349         (operand_entry): New field - 'flags'.
 350         (operand flags): New.
 351
 352         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 353         * crx.h (operand_type): Remove redundant types i3, i4,
 354         i5, i8, i12.
 355         Add new unsigned immediate types us3, us4, us5, us16.
 356
 357 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 358
 359         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 360         adjust them accordingly.
 361
 362 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 363
 364         * i386.h (i386_optab): Add rdtscp.
 365
 366 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 369         between memory and segment register. Allow movq for moving between
 370         general-purpose register and segment register.
 371
 372 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 373
 374         PR gas/707
 375         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 376         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 377         fnstsw.
 378
 379 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 380
 381         * m68k.h (m68008, m68ec030, m68882): Remove.
 382         (m68k_mask): New.
 383         (cpu_m68k, cpu_cf): New.
 384         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 385         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 386
 387 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 388
 389         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 390         * cgen.h (enum cgen_parse_operand_type): Add
 391         CGEN_PARSE_OPERAND_SYMBOLIC.
 392
 393 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 394
 395         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 396         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 397         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 398
 399 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 400
 401         * mips.h (struct mips_opcode): Add new pinfo2 member.
 402         (INSN_ALIAS): New define for opcode table entries that are
 403         specific instances of another entry, such as 'move' for an 'or'
 404         with a zero operand.
 405         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 406         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 407
 408 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 409
 410         * mips.h (CPU_RM9000): Define.
 411         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 412
 413 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 414
 415         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 416         to/from test registers are illegal in 64-bit mode. Add missing
 417         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 418         (previously one had to explicitly encode a rex64 prefix). Re-enable
 419         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 420         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 421
 422 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 423
 424         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 425         available only with SSE2. Change the MMX additions introduced by SSE
 426         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 427         instructions by their now designated identifier (since combining i686
 428         and 3DNow! does not really imply 3DNow!A).
 429
 430 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 431
 432         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 433         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 434
 435 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 436             Vineet Sharma      <vineets@noida.hcltech.com>
 437
 438         * maxq.h: New file: Disassembly information for the maxq port.
 439
 440 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 441
 442         * i386.h (i386_optab): Put back "movzb".
 443
 444 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 445
 446         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 447         comments.  Remove member cris_ver_sim.  Add members
 448         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 449         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 450         (struct cris_support_reg, struct cris_cond15): New types.
 451         (cris_conds15): Declare.
 452         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 453         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 454         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 455         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 456         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 457         SIZE_FIELD_UNSIGNED.
 458
 459 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 460
 461         * i386.h (sldx_Suf): Remove.
 462         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 463         (q_FP): Define, implying no REX64.
 464         (x_FP, sl_FP): Imply FloatMF.
 465         (i386_optab): Split reg and mem forms of moving from segment registers
 466         so that the memory forms can ignore the 16-/32-bit operand size
 467         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 468         all non-floating-point instructions. Unite 32- and 64-bit forms of
 469         movsx, movzx, and movd. Adjust floating point operations for the above
 470         changes to the *FP macros. Add DefaultSize to floating point control
 471         insns operating on larger memory ranges. Remove left over comments
 472         hinting at certain insns being Intel-syntax ones where the ones
 473         actually meant are already gone.
 474
 475 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 476
 477         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 478         instruction type.
 479
 480 2004-09-30  Paul Brook  <paul@codesourcery.com>
 481
 482         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 483         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 484
 485 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 486
 487         * avr.h: Add support for
 488         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 489
 490 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 491
 492         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 493
 494 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 495
 496         * msp430.h (msp430_opc): Add new instructions.
 497         (msp430_rcodes): Declare new instructions.
 498         (msp430_hcodes): Likewise..
 499
 500 2004-08-13  Nick Clifton  <nickc@redhat.com>
 501
 502         PR/301
 503         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 504         processors.
 505
 506 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 507
 508         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 509
 510 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 511
 512         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 513
 514 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 515
 516         * i386.h: Adjust instruction descriptions to better match the
 517         specification.
 518
 519 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 520
 521         * arm.h: Remove all old content.  Replace with architecture defines
 522         from gas/config/tc-arm.c.
 523
 524 2004-07-09  Andreas Schwab  <schwab@suse.de>
 525
 526         * m68k.h: Fix comment.
 527
 528 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 529
 530         * crx.h: New file.
 531
 532 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 533
 534         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 535
 536 2004-05-24  Peter Barada  <peter@the-baradas.com>
 537
 538         * m68k.h: Add 'size' to m68k_opcode.
 539
 540 2004-05-05  Peter Barada  <peter@the-baradas.com>
 541
 542         * m68k.h: Switch from ColdFire chip name to core variant.
 543
 544 2004-04-22  Peter Barada  <peter@the-baradas.com>
 545
 546         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 547         descriptions for new EMAC cases.
 548         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 549         handle Motorola MAC syntax.
 550         Allow disassembly of ColdFire V4e object files.
 551
 552 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 553
 554         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 555
 556 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 557
 558         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 559
 560 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 561
 562         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 563
 564 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 565
 566         * i386.h (i386_optab): Added xstore/xcrypt insns.
 567
 568 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 569
 570         * h8300.h (32bit ldc/stc): Add relaxing support.
 571
 572 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 573
 574         * h8300.h (BITOP): Pass MEMRELAX flag.
 575
 576 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 577
 578         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 579         except for the H8S.
 580
 581 For older changes see ChangeLog-9103
 582 \f
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