include/opcode/ChangeLog

   1 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
   2
   3         * mips.h (INSN_LOONGSON_2E): New.
   4         (INSN_LOONGSON_2F): New.
   5         (CPU_LOONGSON_2E): New.
   6         (CPU_LOONGSON_2F): New.
   7         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
   8
   9 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  10
  11         * mips.h (INSN_ISA*): Redefine certain values as an
  12         enumeration.  Update comments.
  13         (mips_isa_table): New.
  14         (ISA_MIPS*): Redefine to match enumeration.
  15         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
  16         values.
  17
  18 2007-08-08  Ben Elliston  <bje@au.ibm.com>
  19
  20         * ppc.h (PPC_OPCODE_PPCPS): New.
  21
  22 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
  23
  24         * m68k.h: Document j K & E.
  25
  26 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
  27
  28         * cr16.h: New file for CR16 target.
  29
  30 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
  31
  32         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
  33
  34 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
  35
  36         * m68k.h (mcfisa_c): New.
  37         (mcfusp, mcf_mask): Adjust.
  38
  39 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
  40
  41         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
  42         (num_powerpc_operands): Declare.
  43         (PPC_OPERAND_SIGNED et al): Redefine as hex.
  44         (PPC_OPERAND_PLUS1): Define.
  45
  46 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
  47
  48         * i386.h (REX_MODE64): Renamed to ...
  49         (REX_W): This.
  50         (REX_EXTX): Renamed to ...
  51         (REX_R): This.
  52         (REX_EXTY): Renamed to ...
  53         (REX_X): This.
  54         (REX_EXTZ): Renamed to ...
  55         (REX_B): This.
  56
  57 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  58
  59         * i386.h: Add entries from config/tc-i386.h and move tables
  60         to opcodes/i386-opc.h.
  61
  62 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  63
  64         * i386.h (FloatDR): Removed.
  65         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  66
  67 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  68
  69         * spu-insns.h: Add soma double-float insns.
  70
  71 2007-02-20  Thiemo Seufer  <ths@mips.com>
  72             Chao-Ying Fu  <fu@mips.com>
  73
  74         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
  75         (INSN_DSPR2): Add flag for DSP R2 instructions.
  76         (M_BALIGN): New macro.
  77
  78 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  79
  80         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  81         and Seg3ShortFrom with Shortform.
  82
  83 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  84
  85         PR gas/4027
  86         * i386.h (i386_optab): Put the real "test" before the pseudo
  87         one.
  88
  89 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
  90
  91         * m68k.h (m68010up): OR fido_a.
  92
  93 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
  94
  95         * m68k.h (fido_a): New.
  96
  97 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
  98
  99         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 100         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 101         values.
 102
 103 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 104
 105         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 106
 107 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 108
 109         * score-inst.h (enum score_insn_type): Add Insn_internal.
 110
 111 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 112             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 113             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 114             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 115             Alan Modra  <amodra@bigpond.net.au>
 116
 117         * spu-insns.h: New file.
 118         * spu.h: New file.
 119
 120 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 121
 122         * ppc.h (PPC_OPCODE_CELL): Define.
 123
 124 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 125
 126         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 127         in amdfam10 architecture.
 128
 129 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         * i386.h: Replace CpuMNI with CpuSSSE3.
 132
 133 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 134             Joseph Myers  <joseph@codesourcery.com>
 135             Ian Lance Taylor  <ian@wasabisystems.com>
 136             Ben Elliston  <bje@wasabisystems.com>
 137
 138         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 139
 140 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 141
 142         * score-datadep.h: New file.
 143         * score-inst.h: New file.
 144
 145 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 146
 147         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 148         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 149         movdq2q and movq2dq.
 150
 151 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 152            Michael Meissner             <michael.meissner@amd.com>
 153
 154         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 155
 156 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 157
 158         * i386.h (i386_optab): Add "nop" with memory reference.
 159
 160 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 161
 162         * i386.h (i386_optab): Update comment for 64bit NOP.
 163
 164 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 165             Anton Blanchard  <anton@samba.org>
 166
 167         * ppc.h (PPC_OPCODE_POWER6): Define.
 168         Adjust whitespace.
 169
 170 2006-06-05  Thiemo Seufer  <ths@mips.com>
 171
 172         * mips.h: Improve description of MT flags.
 173
 174 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 175
 176         * m68k.h (mcf_mask): Define.
 177
 178 2006-05-05  Thiemo Seufer  <ths@mips.com>
 179             David Ung  <davidu@mips.com>
 180
 181         * mips.h (enum): Add macro M_CACHE_AB.
 182
 183 2006-05-04  Thiemo Seufer  <ths@mips.com>
 184             Nigel Stephens  <nigel@mips.com>
 185             David Ung  <davidu@mips.com>
 186
 187         * mips.h: Add INSN_SMARTMIPS define.
 188
 189 2006-04-30  Thiemo Seufer  <ths@mips.com>
 190             David Ung  <davidu@mips.com>
 191
 192         * mips.h: Defines udi bits and masks.  Add description of
 193         characters which may appear in the args field of udi
 194         instructions.
 195
 196 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 197
 198         * mips.h: Improve comments describing the bitfield instruction
 199         fields.
 200
 201 2006-04-26  Julian Brown  <julian@codesourcery.com>
 202
 203         * arm.h (FPU_VFP_EXT_V3): Define constant.
 204         (FPU_NEON_EXT_V1): Likewise.
 205         (FPU_VFP_HARD): Update.
 206         (FPU_VFP_V3): Define macro.
 207         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 208
 209 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 210
 211         * avr.h (AVR_ISA_PWMx): New.
 212
 213 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 214
 215         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 216         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 217         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 218         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 219         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 220
 221 2006-03-10  Paul Brook  <paul@codesourcery.com>
 222
 223         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 224
 225 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 226
 227         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 228         first.  Correct mask of bb "B" opcode.
 229
 230 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 231
 232         * i386.h (i386_optab): Support Intel Merom New Instructions.
 233
 234 2006-02-24  Paul Brook  <paul@codesourcery.com>
 235
 236         * arm.h: Add V7 feature bits.
 237
 238 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 241
 242 2006-01-31  Paul Brook  <paul@codesourcery.com>
 243         Richard Earnshaw <rearnsha@arm.com>
 244
 245         * arm.h: Use ARM_CPU_FEATURE.
 246         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 247         (arm_feature_set): Change to a structure.
 248         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 249         ARM_FEATURE): New macros.
 250
 251 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 252
 253         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 254         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 255         (ADD_PC_INCR_OPCODE): Don't define.
 256
 257 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         PR gas/1874
 260         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 261
 262 2005-11-14  David Ung  <davidu@mips.com>
 263
 264         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 265         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 266         save/restore encoding of the args field.
 267
 268 2005-10-28  Dave Brolley  <brolley@redhat.com>
 269
 270         Contribute the following changes:
 271         2005-02-16  Dave Brolley  <brolley@redhat.com>
 272
 273         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 274         cgen_isa_mask_* to cgen_bitset_*.
 275         * cgen.h: Likewise.
 276
 277         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 278
 279         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 280         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 281         (CGEN_CPU_TABLE): Make isas a ponter.
 282
 283         2003-09-29  Dave Brolley  <brolley@redhat.com>
 284
 285         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 286         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 287         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 288
 289         2002-12-13  Dave Brolley  <brolley@redhat.com>
 290
 291         * cgen.h (symcat.h): #include it.
 292         (cgen-bitset.h): #include it.
 293         (CGEN_ATTR_VALUE_TYPE): Now a union.
 294         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 295         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 296         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 297         * cgen-bitset.h: New file.
 298
 299 2005-09-30  Catherine Moore  <clm@cm00re.com>
 300
 301         * bfin.h: New file.
 302
 303 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 304
 305         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 306         indirect operands.
 307
 308 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 309
 310         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 311         Add FLAG_STRICT to pa10 ftest opcode.
 312
 313 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 314
 315         * hppa.h (pa_opcodes): Remove lha entries.
 316
 317 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 318
 319         * hppa.h (FLAG_STRICT): Revise comment.
 320         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 321         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 322         entries for "fdc".
 323
 324 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 325
 326         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 327
 328 2005-09-06  Chao-ying Fu  <fu@mips.com>
 329
 330         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 331         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 332         define.
 333         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 334         (INSN_ASE_MASK): Update to include INSN_MT.
 335         (INSN_MT): New define for MT ASE.
 336
 337 2005-08-25  Chao-ying Fu  <fu@mips.com>
 338
 339         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 340         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 341         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 342         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 343         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 344         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 345         instructions.
 346         (INSN_DSP): New define for DSP ASE.
 347
 348 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 349
 350         * a29k.h: Delete.
 351
 352 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 353
 354         * ppc.h (PPC_OPCODE_E300): Define.
 355
 356 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 357
 358         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 359
 360 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 361
 362         PR gas/336
 363         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 364         and pitlb.
 365
 366 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 367
 368         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 369         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 370         Add movq-s as 64-bit variants of movd-s.
 371
 372 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 373
 374         * hppa.h: Fix punctuation in comment.
 375
 376         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 377         implicit space-register addressing.  Set space-register bits on opcodes
 378         using implicit space-register addressing.  Add various missing pa20
 379         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 380         space-register addressing.  Use "fE" instead of "fe" in various
 381         fstw opcodes.
 382
 383 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 384
 385         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 386
 387 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 388
 389         * i386.h (i386_optab): Support Intel VMX Instructions.
 390
 391 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 392
 393         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 394
 395 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 396
 397         * i386.h (i386_optab): Add new insns.
 398
 399 2005-07-01  Nick Clifton  <nickc@redhat.com>
 400
 401         * sparc.h: Add typedefs to structure declarations.
 402
 403 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 404
 405         PR 1013
 406         * i386.h (i386_optab): Update comments for 64bit addressing on
 407         mov. Allow 64bit addressing for mov and movq.
 408
 409 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 410
 411         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 412         respectively, in various floating-point load and store patterns.
 413
 414 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 415
 416         * hppa.h (FLAG_STRICT): Correct comment.
 417         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 418         PA 2.0 mneumonics when equivalent.  Entries with cache control
 419         completers now require PA 1.1.  Adjust whitespace.
 420
 421 2005-05-19  Anton Blanchard  <anton@samba.org>
 422
 423         * ppc.h (PPC_OPCODE_POWER5): Define.
 424
 425 2005-05-10  Nick Clifton  <nickc@redhat.com>
 426
 427         * Update the address and phone number of the FSF organization in
 428         the GPL notices in the following files:
 429         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 430         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 431         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 432         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 433         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 434         tic54x.h, tic80.h, v850.h, vax.h
 435
 436 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 437
 438         * i386.h (i386_optab): Add ht and hnt.
 439
 440 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 441
 442         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 443         Add xcrypt-ctr.  Provide aliases without hyphens.
 444
 445 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         Moved from ../ChangeLog
 448
 449         2005-04-12  Paul Brook  <paul@codesourcery.com>
 450         * m88k.h: Rename psr macros to avoid conflicts.
 451
 452         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 453         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 454         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 455         and ARM_ARCH_V6ZKT2.
 456
 457         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 458         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 459         Remove redundant instruction types.
 460         (struct argument): X_op - new field.
 461         (struct cst4_entry): Remove.
 462         (no_op_insn): Declare.
 463
 464         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 465         * crx.h (enum argtype): Rename types, remove unused types.
 466
 467         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 468         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 469         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 470         (enum operand_type): Rearrange operands, edit comments.
 471         replace us<N> with ui<N> for unsigned immediate.
 472         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 473         displacements (respectively).
 474         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 475         (instruction type): Add NO_TYPE_INS.
 476         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 477         (operand_entry): New field - 'flags'.
 478         (operand flags): New.
 479
 480         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 481         * crx.h (operand_type): Remove redundant types i3, i4,
 482         i5, i8, i12.
 483         Add new unsigned immediate types us3, us4, us5, us16.
 484
 485 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 486
 487         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 488         adjust them accordingly.
 489
 490 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 491
 492         * i386.h (i386_optab): Add rdtscp.
 493
 494 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 495
 496         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 497         between memory and segment register. Allow movq for moving between
 498         general-purpose register and segment register.
 499
 500 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 501
 502         PR gas/707
 503         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 504         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 505         fnstsw.
 506
 507 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 508
 509         * m68k.h (m68008, m68ec030, m68882): Remove.
 510         (m68k_mask): New.
 511         (cpu_m68k, cpu_cf): New.
 512         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 513         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 514
 515 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 516
 517         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 518         * cgen.h (enum cgen_parse_operand_type): Add
 519         CGEN_PARSE_OPERAND_SYMBOLIC.
 520
 521 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 522
 523         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 524         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 525         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 526
 527 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 528
 529         * mips.h (struct mips_opcode): Add new pinfo2 member.
 530         (INSN_ALIAS): New define for opcode table entries that are
 531         specific instances of another entry, such as 'move' for an 'or'
 532         with a zero operand.
 533         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 534         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 535
 536 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 537
 538         * mips.h (CPU_RM9000): Define.
 539         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 540
 541 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 542
 543         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 544         to/from test registers are illegal in 64-bit mode. Add missing
 545         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 546         (previously one had to explicitly encode a rex64 prefix). Re-enable
 547         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 548         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 549
 550 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 551
 552         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 553         available only with SSE2. Change the MMX additions introduced by SSE
 554         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 555         instructions by their now designated identifier (since combining i686
 556         and 3DNow! does not really imply 3DNow!A).
 557
 558 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 559
 560         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 561         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 562
 563 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 564             Vineet Sharma      <vineets@noida.hcltech.com>
 565
 566         * maxq.h: New file: Disassembly information for the maxq port.
 567
 568 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         * i386.h (i386_optab): Put back "movzb".
 571
 572 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 573
 574         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 575         comments.  Remove member cris_ver_sim.  Add members
 576         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 577         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 578         (struct cris_support_reg, struct cris_cond15): New types.
 579         (cris_conds15): Declare.
 580         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 581         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 582         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 583         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 584         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 585         SIZE_FIELD_UNSIGNED.
 586
 587 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 588
 589         * i386.h (sldx_Suf): Remove.
 590         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 591         (q_FP): Define, implying no REX64.
 592         (x_FP, sl_FP): Imply FloatMF.
 593         (i386_optab): Split reg and mem forms of moving from segment registers
 594         so that the memory forms can ignore the 16-/32-bit operand size
 595         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 596         all non-floating-point instructions. Unite 32- and 64-bit forms of
 597         movsx, movzx, and movd. Adjust floating point operations for the above
 598         changes to the *FP macros. Add DefaultSize to floating point control
 599         insns operating on larger memory ranges. Remove left over comments
 600         hinting at certain insns being Intel-syntax ones where the ones
 601         actually meant are already gone.
 602
 603 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 604
 605         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 606         instruction type.
 607
 608 2004-09-30  Paul Brook  <paul@codesourcery.com>
 609
 610         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 611         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 612
 613 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 614
 615         * avr.h: Add support for
 616         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 617
 618 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 619
 620         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 621
 622 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 623
 624         * msp430.h (msp430_opc): Add new instructions.
 625         (msp430_rcodes): Declare new instructions.
 626         (msp430_hcodes): Likewise..
 627
 628 2004-08-13  Nick Clifton  <nickc@redhat.com>
 629
 630         PR/301
 631         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 632         processors.
 633
 634 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 635
 636         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 637
 638 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 639
 640         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 641
 642 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 643
 644         * i386.h: Adjust instruction descriptions to better match the
 645         specification.
 646
 647 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 648
 649         * arm.h: Remove all old content.  Replace with architecture defines
 650         from gas/config/tc-arm.c.
 651
 652 2004-07-09  Andreas Schwab  <schwab@suse.de>
 653
 654         * m68k.h: Fix comment.
 655
 656 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 657
 658         * crx.h: New file.
 659
 660 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 661
 662         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 663
 664 2004-05-24  Peter Barada  <peter@the-baradas.com>
 665
 666         * m68k.h: Add 'size' to m68k_opcode.
 667
 668 2004-05-05  Peter Barada  <peter@the-baradas.com>
 669
 670         * m68k.h: Switch from ColdFire chip name to core variant.
 671
 672 2004-04-22  Peter Barada  <peter@the-baradas.com>
 673
 674         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 675         descriptions for new EMAC cases.
 676         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 677         handle Motorola MAC syntax.
 678         Allow disassembly of ColdFire V4e object files.
 679
 680 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 681
 682         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 683
 684 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 685
 686         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 687
 688 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 689
 690         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 691
 692 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 693
 694         * i386.h (i386_optab): Added xstore/xcrypt insns.
 695
 696 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 697
 698         * h8300.h (32bit ldc/stc): Add relaxing support.
 699
 700 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 701
 702         * h8300.h (BITOP): Pass MEMRELAX flag.
 703
 704 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 705
 706         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 707         except for the H8S.
 708
 709 For older changes see ChangeLog-9103
 710 \f
 711 Local Variables:
 712 mode: change-log
 713 left-margin: 8
 714 fill-column: 74
 715 version-control: never
 716 End: