include/opcode/ChangeLog

   1 2008-11-18  Catherine Moore  <clm@codesourcery.com>
   2
   3         * arm.h (FPU_NEON_FP16): New.
   4         (FPU_ARCH_NEON_FP16): New.
   5
   6 2008-11-06  Chao-ying Fu  <fu@mips.com>
   7
   8         * mips.h: Doucument '1' for 5-bit sync type.
   9
  10 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
  13         IA64_RS_CR.
  14
  15 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
  16
  17         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
  18
  19 2008-07-30  Michael J. Eager  <eager@eagercon.com>
  20
  21         * ppc.h (PPC_OPCODE_405): Define.
  22         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
  23
  24 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
  25
  26         * ppc.h (ppc_cpu_t): New typedef.
  27         (struct powerpc_opcode <flags>): Use it.
  28         (struct powerpc_operand <insert, extract>): Likewise.
  29         (struct powerpc_macro <flags>): Likewise.
  30
  31 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
  32
  33         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
  34         Update comment before MIPS16 field descriptors to mention MIPS16.
  35         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
  36         BBIT.
  37         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
  38         New bit masks and shift counts for cins and exts.
  39
  40         * mips.h: Document new field descriptors +Q.
  41         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
  42
  43 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
  44
  45         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
  46         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
  47
  48 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
  49
  50         * ppc.h: (PPC_OPCODE_E500MC): New.
  51
  52 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
  53
  54         * i386.h (MAX_OPERANDS): Set to 5.
  55         (MAX_MNEM_SIZE): Changed to 20.
  56
  57 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
  58
  59         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
  60
  61 2008-03-09  Paul Brook  <paul@codesourcery.com>
  62
  63         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
  64
  65 2008-03-04  Paul Brook  <paul@codesourcery.com>
  66
  67         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
  68         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
  69         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
  70
  71 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
  72             Nick Clifton  <nickc@redhat.com>
  73
  74         PR 3134
  75         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
  76         with a 32-bit displacement but without the top bit of the 4th byte
  77         set.
  78
  79 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
  80
  81         * cr16.h (cr16_num_optab): Declared.
  82
  83 2008-02-14  Hakan Ardo  <hakan@debian.org>
  84
  85         PR gas/2626
  86         * avr.h (AVR_ISA_2xxe): Define.
  87
  88 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
  89
  90         * mips.h: Update copyright.
  91         (INSN_CHIP_MASK): New macro.
  92         (INSN_OCTEON): New macro.
  93         (CPU_OCTEON): New macro.
  94         (OPCODE_IS_MEMBER): Handle Octeon instructions.
  95
  96 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
  97
  98         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
  99
 100 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 101
 102         * avr.h (AVR_ISA_USB162): Add new opcode set.
 103         (AVR_ISA_AVR3): Likewise.
 104
 105 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 106
 107         * mips.h (INSN_LOONGSON_2E): New.
 108         (INSN_LOONGSON_2F): New.
 109         (CPU_LOONGSON_2E): New.
 110         (CPU_LOONGSON_2F): New.
 111         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 112
 113 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 114
 115         * mips.h (INSN_ISA*): Redefine certain values as an
 116         enumeration.  Update comments.
 117         (mips_isa_table): New.
 118         (ISA_MIPS*): Redefine to match enumeration.
 119         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 120         values.
 121
 122 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 123
 124         * ppc.h (PPC_OPCODE_PPCPS): New.
 125
 126 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 127
 128         * m68k.h: Document j K & E.
 129
 130 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 131
 132         * cr16.h: New file for CR16 target.
 133
 134 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 135
 136         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 137
 138 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 139
 140         * m68k.h (mcfisa_c): New.
 141         (mcfusp, mcf_mask): Adjust.
 142
 143 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 144
 145         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 146         (num_powerpc_operands): Declare.
 147         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 148         (PPC_OPERAND_PLUS1): Define.
 149
 150 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 151
 152         * i386.h (REX_MODE64): Renamed to ...
 153         (REX_W): This.
 154         (REX_EXTX): Renamed to ...
 155         (REX_R): This.
 156         (REX_EXTY): Renamed to ...
 157         (REX_X): This.
 158         (REX_EXTZ): Renamed to ...
 159         (REX_B): This.
 160
 161 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 162
 163         * i386.h: Add entries from config/tc-i386.h and move tables
 164         to opcodes/i386-opc.h.
 165
 166 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 167
 168         * i386.h (FloatDR): Removed.
 169         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 170
 171 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 172
 173         * spu-insns.h: Add soma double-float insns.
 174
 175 2007-02-20  Thiemo Seufer  <ths@mips.com>
 176             Chao-Ying Fu  <fu@mips.com>
 177
 178         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 179         (INSN_DSPR2): Add flag for DSP R2 instructions.
 180         (M_BALIGN): New macro.
 181
 182 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 183
 184         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 185         and Seg3ShortFrom with Shortform.
 186
 187 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         PR gas/4027
 190         * i386.h (i386_optab): Put the real "test" before the pseudo
 191         one.
 192
 193 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 194
 195         * m68k.h (m68010up): OR fido_a.
 196
 197 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 198
 199         * m68k.h (fido_a): New.
 200
 201 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 202
 203         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 204         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 205         values.
 206
 207 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 210
 211 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 212
 213         * score-inst.h (enum score_insn_type): Add Insn_internal.
 214
 215 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 216             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 217             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 218             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 219             Alan Modra  <amodra@bigpond.net.au>
 220
 221         * spu-insns.h: New file.
 222         * spu.h: New file.
 223
 224 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 225
 226         * ppc.h (PPC_OPCODE_CELL): Define.
 227
 228 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 229
 230         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 231         in amdfam10 architecture.
 232
 233 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 234
 235         * i386.h: Replace CpuMNI with CpuSSSE3.
 236
 237 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 238             Joseph Myers  <joseph@codesourcery.com>
 239             Ian Lance Taylor  <ian@wasabisystems.com>
 240             Ben Elliston  <bje@wasabisystems.com>
 241
 242         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 243
 244 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 245
 246         * score-datadep.h: New file.
 247         * score-inst.h: New file.
 248
 249 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 252         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 253         movdq2q and movq2dq.
 254
 255 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 256            Michael Meissner             <michael.meissner@amd.com>
 257
 258         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 259
 260 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 261
 262         * i386.h (i386_optab): Add "nop" with memory reference.
 263
 264 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 265
 266         * i386.h (i386_optab): Update comment for 64bit NOP.
 267
 268 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 269             Anton Blanchard  <anton@samba.org>
 270
 271         * ppc.h (PPC_OPCODE_POWER6): Define.
 272         Adjust whitespace.
 273
 274 2006-06-05  Thiemo Seufer  <ths@mips.com>
 275
 276         * mips.h: Improve description of MT flags.
 277
 278 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 279
 280         * m68k.h (mcf_mask): Define.
 281
 282 2006-05-05  Thiemo Seufer  <ths@mips.com>
 283             David Ung  <davidu@mips.com>
 284
 285         * mips.h (enum): Add macro M_CACHE_AB.
 286
 287 2006-05-04  Thiemo Seufer  <ths@mips.com>
 288             Nigel Stephens  <nigel@mips.com>
 289             David Ung  <davidu@mips.com>
 290
 291         * mips.h: Add INSN_SMARTMIPS define.
 292
 293 2006-04-30  Thiemo Seufer  <ths@mips.com>
 294             David Ung  <davidu@mips.com>
 295
 296         * mips.h: Defines udi bits and masks.  Add description of
 297         characters which may appear in the args field of udi
 298         instructions.
 299
 300 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 301
 302         * mips.h: Improve comments describing the bitfield instruction
 303         fields.
 304
 305 2006-04-26  Julian Brown  <julian@codesourcery.com>
 306
 307         * arm.h (FPU_VFP_EXT_V3): Define constant.
 308         (FPU_NEON_EXT_V1): Likewise.
 309         (FPU_VFP_HARD): Update.
 310         (FPU_VFP_V3): Define macro.
 311         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 312
 313 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 314
 315         * avr.h (AVR_ISA_PWMx): New.
 316
 317 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 318
 319         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 320         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 321         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 322         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 323         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 324
 325 2006-03-10  Paul Brook  <paul@codesourcery.com>
 326
 327         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 328
 329 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 330
 331         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 332         first.  Correct mask of bb "B" opcode.
 333
 334 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 335
 336         * i386.h (i386_optab): Support Intel Merom New Instructions.
 337
 338 2006-02-24  Paul Brook  <paul@codesourcery.com>
 339
 340         * arm.h: Add V7 feature bits.
 341
 342 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 343
 344         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 345
 346 2006-01-31  Paul Brook  <paul@codesourcery.com>
 347         Richard Earnshaw <rearnsha@arm.com>
 348
 349         * arm.h: Use ARM_CPU_FEATURE.
 350         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 351         (arm_feature_set): Change to a structure.
 352         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 353         ARM_FEATURE): New macros.
 354
 355 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 356
 357         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 358         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 359         (ADD_PC_INCR_OPCODE): Don't define.
 360
 361 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 362
 363         PR gas/1874
 364         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 365
 366 2005-11-14  David Ung  <davidu@mips.com>
 367
 368         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 369         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 370         save/restore encoding of the args field.
 371
 372 2005-10-28  Dave Brolley  <brolley@redhat.com>
 373
 374         Contribute the following changes:
 375         2005-02-16  Dave Brolley  <brolley@redhat.com>
 376
 377         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 378         cgen_isa_mask_* to cgen_bitset_*.
 379         * cgen.h: Likewise.
 380
 381         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 382
 383         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 384         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 385         (CGEN_CPU_TABLE): Make isas a ponter.
 386
 387         2003-09-29  Dave Brolley  <brolley@redhat.com>
 388
 389         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 390         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 391         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 392
 393         2002-12-13  Dave Brolley  <brolley@redhat.com>
 394
 395         * cgen.h (symcat.h): #include it.
 396         (cgen-bitset.h): #include it.
 397         (CGEN_ATTR_VALUE_TYPE): Now a union.
 398         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 399         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 400         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 401         * cgen-bitset.h: New file.
 402
 403 2005-09-30  Catherine Moore  <clm@cm00re.com>
 404
 405         * bfin.h: New file.
 406
 407 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 408
 409         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 410         indirect operands.
 411
 412 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 413
 414         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 415         Add FLAG_STRICT to pa10 ftest opcode.
 416
 417 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 418
 419         * hppa.h (pa_opcodes): Remove lha entries.
 420
 421 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 422
 423         * hppa.h (FLAG_STRICT): Revise comment.
 424         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 425         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 426         entries for "fdc".
 427
 428 2005-09-30  Catherine Moore  <clm@cm00re.com>
 429
 430         * bfin.h: New file.
 431
 432 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 433
 434         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 435
 436 2005-09-06  Chao-ying Fu  <fu@mips.com>
 437
 438         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 439         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 440         define.
 441         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 442         (INSN_ASE_MASK): Update to include INSN_MT.
 443         (INSN_MT): New define for MT ASE.
 444
 445 2005-08-25  Chao-ying Fu  <fu@mips.com>
 446
 447         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 448         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 449         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 450         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 451         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 452         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 453         instructions.
 454         (INSN_DSP): New define for DSP ASE.
 455
 456 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 457
 458         * a29k.h: Delete.
 459
 460 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 461
 462         * ppc.h (PPC_OPCODE_E300): Define.
 463
 464 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 465
 466         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 467
 468 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 469
 470         PR gas/336
 471         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 472         and pitlb.
 473
 474 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 475
 476         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 477         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 478         Add movq-s as 64-bit variants of movd-s.
 479
 480 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 481
 482         * hppa.h: Fix punctuation in comment.
 483
 484         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 485         implicit space-register addressing.  Set space-register bits on opcodes
 486         using implicit space-register addressing.  Add various missing pa20
 487         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 488         space-register addressing.  Use "fE" instead of "fe" in various
 489         fstw opcodes.
 490
 491 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 492
 493         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 494
 495 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 496
 497         * i386.h (i386_optab): Support Intel VMX Instructions.
 498
 499 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 500
 501         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 502
 503 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 504
 505         * i386.h (i386_optab): Add new insns.
 506
 507 2005-07-01  Nick Clifton  <nickc@redhat.com>
 508
 509         * sparc.h: Add typedefs to structure declarations.
 510
 511 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 512
 513         PR 1013
 514         * i386.h (i386_optab): Update comments for 64bit addressing on
 515         mov. Allow 64bit addressing for mov and movq.
 516
 517 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 518
 519         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 520         respectively, in various floating-point load and store patterns.
 521
 522 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 523
 524         * hppa.h (FLAG_STRICT): Correct comment.
 525         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 526         PA 2.0 mneumonics when equivalent.  Entries with cache control
 527         completers now require PA 1.1.  Adjust whitespace.
 528
 529 2005-05-19  Anton Blanchard  <anton@samba.org>
 530
 531         * ppc.h (PPC_OPCODE_POWER5): Define.
 532
 533 2005-05-10  Nick Clifton  <nickc@redhat.com>
 534
 535         * Update the address and phone number of the FSF organization in
 536         the GPL notices in the following files:
 537         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 538         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 539         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 540         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 541         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 542         tic54x.h, tic80.h, v850.h, vax.h
 543
 544 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 545
 546         * i386.h (i386_optab): Add ht and hnt.
 547
 548 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 549
 550         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 551         Add xcrypt-ctr.  Provide aliases without hyphens.
 552
 553 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 554
 555         Moved from ../ChangeLog
 556
 557         2005-04-12  Paul Brook  <paul@codesourcery.com>
 558         * m88k.h: Rename psr macros to avoid conflicts.
 559
 560         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 561         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 562         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 563         and ARM_ARCH_V6ZKT2.
 564
 565         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 566         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 567         Remove redundant instruction types.
 568         (struct argument): X_op - new field.
 569         (struct cst4_entry): Remove.
 570         (no_op_insn): Declare.
 571
 572         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 573         * crx.h (enum argtype): Rename types, remove unused types.
 574
 575         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 576         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 577         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 578         (enum operand_type): Rearrange operands, edit comments.
 579         replace us<N> with ui<N> for unsigned immediate.
 580         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 581         displacements (respectively).
 582         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 583         (instruction type): Add NO_TYPE_INS.
 584         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 585         (operand_entry): New field - 'flags'.
 586         (operand flags): New.
 587
 588         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 589         * crx.h (operand_type): Remove redundant types i3, i4,
 590         i5, i8, i12.
 591         Add new unsigned immediate types us3, us4, us5, us16.
 592
 593 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 594
 595         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 596         adjust them accordingly.
 597
 598 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 599
 600         * i386.h (i386_optab): Add rdtscp.
 601
 602 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 603
 604         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 605         between memory and segment register. Allow movq for moving between
 606         general-purpose register and segment register.
 607
 608 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 609
 610         PR gas/707
 611         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 612         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 613         fnstsw.
 614
 615 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 616
 617         * m68k.h (m68008, m68ec030, m68882): Remove.
 618         (m68k_mask): New.
 619         (cpu_m68k, cpu_cf): New.
 620         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 621         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 622
 623 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 624
 625         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 626         * cgen.h (enum cgen_parse_operand_type): Add
 627         CGEN_PARSE_OPERAND_SYMBOLIC.
 628
 629 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 630
 631         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 632         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 633         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 634
 635 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 636
 637         * mips.h (struct mips_opcode): Add new pinfo2 member.
 638         (INSN_ALIAS): New define for opcode table entries that are
 639         specific instances of another entry, such as 'move' for an 'or'
 640         with a zero operand.
 641         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 642         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 643
 644 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 645
 646         * mips.h (CPU_RM9000): Define.
 647         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 648
 649 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 650
 651         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 652         to/from test registers are illegal in 64-bit mode. Add missing
 653         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 654         (previously one had to explicitly encode a rex64 prefix). Re-enable
 655         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 656         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 657
 658 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 659
 660         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 661         available only with SSE2. Change the MMX additions introduced by SSE
 662         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 663         instructions by their now designated identifier (since combining i686
 664         and 3DNow! does not really imply 3DNow!A).
 665
 666 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 667
 668         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 669         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 670
 671 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 672             Vineet Sharma      <vineets@noida.hcltech.com>
 673
 674         * maxq.h: New file: Disassembly information for the maxq port.
 675
 676 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 677
 678         * i386.h (i386_optab): Put back "movzb".
 679
 680 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 681
 682         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 683         comments.  Remove member cris_ver_sim.  Add members
 684         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 685         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 686         (struct cris_support_reg, struct cris_cond15): New types.
 687         (cris_conds15): Declare.
 688         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 689         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 690         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 691         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 692         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 693         SIZE_FIELD_UNSIGNED.
 694
 695 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 696
 697         * i386.h (sldx_Suf): Remove.
 698         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 699         (q_FP): Define, implying no REX64.
 700         (x_FP, sl_FP): Imply FloatMF.
 701         (i386_optab): Split reg and mem forms of moving from segment registers
 702         so that the memory forms can ignore the 16-/32-bit operand size
 703         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 704         all non-floating-point instructions. Unite 32- and 64-bit forms of
 705         movsx, movzx, and movd. Adjust floating point operations for the above
 706         changes to the *FP macros. Add DefaultSize to floating point control
 707         insns operating on larger memory ranges. Remove left over comments
 708         hinting at certain insns being Intel-syntax ones where the ones
 709         actually meant are already gone.
 710
 711 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 712
 713         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 714         instruction type.
 715
 716 2004-09-30  Paul Brook  <paul@codesourcery.com>
 717
 718         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 719         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 720
 721 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 722
 723         * avr.h: Add support for
 724         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 725
 726 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 727
 728         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 729
 730 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 731
 732         * msp430.h (msp430_opc): Add new instructions.
 733         (msp430_rcodes): Declare new instructions.
 734         (msp430_hcodes): Likewise..
 735
 736 2004-08-13  Nick Clifton  <nickc@redhat.com>
 737
 738         PR/301
 739         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 740         processors.
 741
 742 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 743
 744         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 745
 746 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 747
 748         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 749
 750 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 751
 752         * i386.h: Adjust instruction descriptions to better match the
 753         specification.
 754
 755 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 756
 757         * arm.h: Remove all old content.  Replace with architecture defines
 758         from gas/config/tc-arm.c.
 759
 760 2004-07-09  Andreas Schwab  <schwab@suse.de>
 761
 762         * m68k.h: Fix comment.
 763
 764 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 765
 766         * crx.h: New file.
 767
 768 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 769
 770         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 771
 772 2004-05-24  Peter Barada  <peter@the-baradas.com>
 773
 774         * m68k.h: Add 'size' to m68k_opcode.
 775
 776 2004-05-05  Peter Barada  <peter@the-baradas.com>
 777
 778         * m68k.h: Switch from ColdFire chip name to core variant.
 779
 780 2004-04-22  Peter Barada  <peter@the-baradas.com>
 781
 782         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 783         descriptions for new EMAC cases.
 784         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 785         handle Motorola MAC syntax.
 786         Allow disassembly of ColdFire V4e object files.
 787
 788 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 789
 790         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 791
 792 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 793
 794         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 795
 796 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 797
 798         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 799
 800 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 801
 802         * i386.h (i386_optab): Added xstore/xcrypt insns.
 803
 804 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 805
 806         * h8300.h (32bit ldc/stc): Add relaxing support.
 807
 808 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 809
 810         * h8300.h (BITOP): Pass MEMRELAX flag.
 811
 812 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 813
 814         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 815         except for the H8S.
 816
 817 For older changes see ChangeLog-9103
 818 \f
 819 Local Variables:
 820 mode: change-log
 821 left-margin: 8
 822 fill-column: 74
 823 version-control: never
 824 End: