include/opcode/ChangeLog

   1 2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
   2
   3         * arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
   4         (ARM_AEXT2_V8A): New architecture extension bitfield.
   5         (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
   6         (ARM_AEXT_V8M_BASE): New architecture extension bitfield.
   7         (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
   8         (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
   9         bitfield.
  10         (ARM_ARCH_V6KT2): Likewise.
  11         (ARM_ARCH_V6ZT2): Likewise.
  12         (ARM_ARCH_V6KZT2): Likewise.
  13         (ARM_ARCH_V7): Likewise.
  14         (ARM_ARCH_V7A): Likewise.
  15         (ARM_ARCH_V7VE): Likewise.
  16         (ARM_ARCH_V7R): Likewise.
  17         (ARM_ARCH_V7M): Likewise.
  18         (ARM_ARCH_V7EM): Likewise.
  19         (ARM_ARCH_V8A): Likewise.
  20         (ARM_ARCH_V8M_BASE): New architecture bitfield.
  21         (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
  22         (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
  23         bitfield and reindent.
  24         (ARM_ARCH_V7A_MP_SEC): Likewise.
  25         (ARM_ARCH_V7R_IDIV): Likewise.
  26         (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
  27         (ARM_ARCH_V8A_SIMD): Likewise.
  28         (ARM_ARCH_V8A_CRYPTOV1): Likewise.
  29
  30 2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  31
  32         * arm.h (ARM_EXT2_ATOMICS): New extension bit.
  33         (ARM_EXT2_V8M): Likewise.
  34         (ARM_EXT_V8): Adjust comment with regards to atomics and remove
  35         mention of legacy use for that bit.
  36         (ARM_AEXT2_V8_1A): New architecture extension bitfield.
  37         (ARM_AEXT2_V8_2A): Likewise.
  38         (ARM_AEXT_V8M_MAIN): Likewise.
  39         (ARM_AEXT2_V8M): Likewise.
  40         (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
  41         (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
  42         (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
  43         (ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
  44         (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
  45         and reindent.
  46         (ARM_ARCH_V8A_SIMD): Likewise.
  47         (ARM_ARCH_V8A_CRYPTOV1): Likewise.
  48         (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
  49         feature bits.
  50         (ARM_ARCH_V8_1A_SIMD): Likewise.
  51         (ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
  52
  53 2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  54
  55         * arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
  56         remove extension bit not including any Thumb-2 instruction.
  57
  58 2015-12-15  Matthew Wahab  <matthew.wahab@arm.com>
  59
  60         * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
  61         feature macro.
  62         (ARM_ARCH_V8_2A): Likewise.
  63
  64 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  65
  66         * aarch64.h (enum aarch64_opnd_qualifier): Add
  67         AARCH64_OPND_QLF_V_2H.
  68
  69 2015-12-14  Yoshinori Sato <ysato@users.sourceforge.jp>
  70
  71         * rx.h: Add new instructions.
  72
  73 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  74
  75         * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
  76         * aarch64-asm-2.c: Regenerate.
  77         * aarch64-dis-2.c: Regenerate.
  78         * aarch64-opc-2.c: Regenerate.
  79         * aarch64-opc.c (aarch64_hint_options): Add "csync".
  80         (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
  81         * aarch64-tbl.h (aarch64_feature_stat_profile): New.
  82         (STAT_PROFILE): New.
  83         (aarch64_opcode_table): Add "psb".
  84         (AARCH64_OPERANDS): Add "BARRIER_PSB".
  85
  86 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  87
  88         * aarch64.h (aarch64_hint_options): Declare.
  89         (aarch64_opnd_info): Add field hint_option.
  90
  91 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  92
  93         * aarch64.h (AARCH64_FEATURE_PROFILE): New.
  94
  95 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  96
  97         * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
  98
  99 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 100
 101         * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
 102         (aarch64_sys_ins_reg_has_xt): Declare.
 103
 104 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 105
 106         * aarch64.h (AARCH64_FEATURE_RAS): New.
 107         (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
 108
 109 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 110
 111         * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
 112         AARCH64_FEATURE_V8_1.
 113         (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
 114         (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
 115         AARCH64_FEATURE_V8_1.
 116
 117 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 118
 119         * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
 120
 121 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 122
 123         * aarch64.h (aarch64_op): Add OP_BFC.
 124
 125 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 126
 127         * aarch64.h (AARCH64_FEATURE_F16): New.
 128         (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
 129         features.
 130
 131 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 132
 133         * aarch64.h (AARCH64_FEATURE_V8_1): New.
 134         (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
 135
 136 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 137
 138         * arm.h (ARM_EXT2_V8_2A): New.
 139         (ARM_ARCH_V8_2A): New.
 140
 141 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 142
 143         * aarch64.h (AARCH64_FEATURE_V8_2): New.
 144         (AARCH64_ARCH_V8_2): New.
 145
 146 2015-11-11  Alan Modra  <amodra@gmail.com>
 147             Peter Bergner <bergner@vnet.ibm.com>
 148
 149         * ppc.h (PPC_OPCODE_POWER9): New define.
 150         (PPC_OPCODE_VSX3): Likewise.
 151
 152 2015-11-02  Nick Clifton  <nickc@redhat.com>
 153
 154         * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
 155
 156 2015-11-02  Nick Clifton  <nickc@redhat.com>
 157
 158         * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
 159
 160 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 161
 162         * aarch64.h (aarch64_decode_insn): Update declaration.
 163
 164 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 165
 166         * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
 167         <name>: New field.
 168
 169 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 170
 171         * aarch64.h [__cplusplus]: Wrap in extern "C".
 172
 173 2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
 174             Cupertino Miranda  <cmiranda@synopsys.com>
 175
 176         * arc-func.h: New file.
 177         * arc.h: Likewise.
 178
 179 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 180
 181         * aarch64.h (aarch64_zero_register_p): Move the declaration
 182         to column one.
 183
 184 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 185
 186         * aarch64.h (aarch64_decode_insn): Declare it.
 187
 188 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 189
 190         * s390.h (S390_INSTR_FLAG_HTM): New flag.
 191         (S390_INSTR_FLAG_VX): New flag.
 192         (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
 193
 194 2015-09-23  Nick Clifton  <nickc@redhat.com>
 195
 196         * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
 197         shifting.
 198
 199 2015-09-22  Nick Clifton  <nickc@redhat.com>
 200
 201         * rx.h (enum RX_Size): Add RX_Bad_Size entry.
 202
 203 2015-09-09  Daniel Santos  <daniel.santos@pobox.com>
 204
 205         * visium.h (gen_reg_table): Make static.
 206         (fp_reg_table): Likewise.
 207         (cc_table): Likewise.
 208
 209 2015-07-20  Matthew Wahab  <matthew.wahab@arm.com>
 210
 211         * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
 212         (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
 213         (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
 214         (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
 215
 216 2015-07-03  Alan Modra  <amodra@gmail.com>
 217
 218         * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
 219
 220 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 221             Cesar Philippidis  <cesar@codesourcery.com>
 222
 223         * nios2.h (enum iw_format_type): Add R2 formats.
 224         (enum overflow_type): Add signed_immed12_overflow and
 225         enumeration_overflow for R2.
 226         (struct nios2_opcode): Document new argument letters for R2.
 227         (REG_3BIT, REG_LDWM, REG_POP): Define.
 228         (includes): Include nios2r2.h.
 229         (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
 230         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
 231         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
 232         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
 233         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
 234         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
 235         Declare.
 236         * nios2r2.h: New file.
 237
 238 2015-06-19  Peter Bergner <bergner@vnet.ibm.com>
 239
 240         * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
 241         (ppc_optional_operand_value): New inline function.
 242
 243 2015-06-04  Matthew Wahab  <matthew.wahab@arm.com>
 244
 245         * aarch64.h (AARCH64_V8_1): New.
 246
 247 2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>
 248
 249         * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
 250         (ARM_ARCH_V8_1A): New.
 251         (ARM_ARCH_V8_1A_FP): New.
 252         (ARM_ARCH_V8_1A_SIMD): New.
 253         (ARM_ARCH_V8_1A_CRYPTOV1): New.
 254         (ARM_FEATURE_CORE): New.
 255
 256 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 257
 258         * arm.h (ARM_EXT2_PAN): New.
 259         (ARM_FEATURE_CORE_HIGH): New.
 260
 261 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 262
 263         * arm.h (ARM_FEATURE_ALL): New.
 264
 265 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 266
 267         * aarch64.h (AARCH64_FEATURE_RDMA): New.
 268
 269 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 270
 271         * aarch64.h (AARCH64_FEATURE_LOR): New.
 272
 273 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 274
 275         * aarch64.h (AARCH64_FEATURE_PAN): New.
 276         (aarch64_sys_reg_supported_p): Declare.
 277         (aarch64_pstatefield_supported_p): Declare.
 278
 279 2015-04-30  DJ Delorie  <dj@redhat.com>
 280
 281         * rl78.h (RL78_Dis_Isa): New.
 282         (rl78_decode_opcode): Add ISA parameter.
 283
 284 2015-03-24  Terry Guo  <terry.guo@arm.com>
 285
 286         * arm.h (arm_feature_set): Extended to provide more available bits.
 287         (ARM_ANY): Updated to follow above new definition.
 288         (ARM_CPU_HAS_FEATURE): Likewise.
 289         (ARM_CPU_IS_ANY): Likewise.
 290         (ARM_MERGE_FEATURE_SETS): Likewise.
 291         (ARM_CLEAR_FEATURE): Likewise.
 292         (ARM_FEATURE): Likewise.
 293         (ARM_FEATURE_COPY): New macro.
 294         (ARM_FEATURE_EQUAL): Likewise.
 295         (ARM_FEATURE_ZERO): Likewise.
 296         (ARM_FEATURE_CORE_EQUAL): Likewise.
 297         (ARM_FEATURE_LOW): Likewise.
 298         (ARM_FEATURE_CORE_LOW): Likewise.
 299         (ARM_FEATURE_CORE_COPROC): Likewise.
 300
 301 2015-02-19  Pedro Alves  <palves@redhat.com>
 302
 303         * cgen.h [__cplusplus]: Wrap in extern "C".
 304         * msp430-decode.h [__cplusplus]: Likewise.
 305         * nios2.h [__cplusplus]: Likewise.
 306         * rl78.h [__cplusplus]: Likewise.
 307         * rx.h [__cplusplus]: Likewise.
 308         * tilegx.h [__cplusplus]: Likewise.
 309
 310 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 311
 312         * ft32.h: New file.
 313
 314 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 315
 316         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
 317
 318 2015-01-01  Alan Modra  <amodra@gmail.com>
 319
 320         Update year range in copyright notice of all files.
 321
 322 2014-12-27  Anthony Green  <green@moxielogic.com>
 323
 324         * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
 325         MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
 326
 327 2014-12-06  Eric Botcazou  <ebotcazou@adacore.com>
 328
 329         * visium.h: New file.
 330
 331 2014-11-28  Sandra Loosemore  <sandra@codesourcery.com>
 332
 333         * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
 334         (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
 335         (NIOS2_INSN_OPTARG): Renumber.
 336
 337 2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
 338
 339         * nios2.h (nios2_find_opcode_hash): Add mach parameter to
 340         declaration.  Fix obsolete comment.
 341
 342 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
 343
 344         * nios2.h (enum iw_format_type): New.
 345         (struct nios2_opcode): Update comments.  Add size and format fields.
 346         (NIOS2_INSN_OPTARG): New.
 347         (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
 348         (struct nios2_reg): Add regtype field.
 349         (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
 350         (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
 351         (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
 352         (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
 353         (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
 354         (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
 355         (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
 356         (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
 357         (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
 358         (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
 359         (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
 360         (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
 361         (OP_MASK_OP, OP_SH_OP): Delete.
 362         (OP_MASK_IOP, OP_SH_IOP): Delete.
 363         (OP_MASK_IRD, OP_SH_IRD): Delete.
 364         (OP_MASK_IRT, OP_SH_IRT): Delete.
 365         (OP_MASK_IRS, OP_SH_IRS): Delete.
 366         (OP_MASK_ROP, OP_SH_ROP): Delete.
 367         (OP_MASK_RRD, OP_SH_RRD): Delete.
 368         (OP_MASK_RRT, OP_SH_RRT): Delete.
 369         (OP_MASK_RRS, OP_SH_RRS): Delete.
 370         (OP_MASK_JOP, OP_SH_JOP): Delete.
 371         (OP_MASK_IMM26, OP_SH_IMM26): Delete.
 372         (OP_MASK_RCTL, OP_SH_RCTL): Delete.
 373         (OP_MASK_IMM5, OP_SH_IMM5): Delete.
 374         (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
 375         (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
 376         (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
 377         (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
 378         (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
 379         (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
 380         (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
 381         (OP_MASK_<insn>, OP_MASK): Delete.
 382         (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
 383         (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
 384         Include nios2r1.h to define new instruction opcode constants
 385         and accessors.
 386         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
 387         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
 388         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
 389         (NUMOPCODES, NUMREGISTERS): Delete.
 390         * nios2r1.h: New file.
 391
 392 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 393
 394         * sparc.h (HWCAP2_VIS3B): Documentation improved.
 395
 396 2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 397
 398         * sparc.h (sparc_opcode): new field `hwcaps2'.
 399         (HWCAP2_FJATHPLUS): New define.
 400         (HWCAP2_VIS3B): Likewise.
 401         (HWCAP2_ADP): Likewise.
 402         (HWCAP2_SPARC5): Likewise.
 403         (HWCAP2_MWAIT): Likewise.
 404         (HWCAP2_XMPMUL): Likewise.
 405         (HWCAP2_XMONT): Likewise.
 406         (HWCAP2_NSEC): Likewise.
 407         (HWCAP2_FJATHHPC): Likewise.
 408         (HWCAP2_FJDES): Likewise.
 409         (HWCAP2_FJAES): Likewise.
 410         Document the new operand kind `{', corresponding to the mcdper
 411         ancillary state register.
 412         Document the new operand kind }, which represents frsd floating
 413         point registers (double precision) which must be the same than
 414         frs1 in its containing instruction.
 415
 416 2014-09-16  Kuan-Lin Chen <kuanlinchentw@gmail.com>
 417
 418         * nds32.h: Add new opcode declaration.
 419
 420 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 421             Matthew Fortune  <matthew.fortune@imgtec.com>
 422
 423         * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
 424         OP_CHECK_PREV and OP_NON_ZERO_REG.  Add descriptions for the MIPS R6
 425         instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
 426          +I, +O, +R, +:, +\, +", +;
 427         (mips_check_prev_operand): New struct.
 428         (INSN2_FORBIDDEN_SLOT): New define.
 429         (INSN_ISA32R6): New define.
 430         (INSN_ISA64R6): New define.
 431         (INSN_UPTO32R6): New define.
 432         (INSN_UPTO64R6): New define.
 433         (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
 434         (ISA_MIPS32R6): New define.
 435         (ISA_MIPS64R6): New define.
 436         (CPU_MIPS32R6): New define.
 437         (CPU_MIPS64R6): New define.
 438         (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
 439
 440 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 441
 442         * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
 443         (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
 444         (aarch64_insn_class): Add lse_atomic.
 445         (F_LSE_SZ): New field added.
 446         (opcode_has_special_coder): Recognize F_LSE_SZ.
 447
 448 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 449
 450         * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
 451         over to `+J'.
 452
 453 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 454
 455         * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
 456         (INSN_LOAD_COPROC): New define.
 457         (INSN_COPROC_MOVE_DELAY): Rename to...
 458         (INSN_COPROC_MOVE): New define.
 459
 460 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 461             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 462             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 463             Soundararajan  <Sounderarajan.D@atmel.com>
 464
 465         * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
 466         (AVR_ISA_2xxxa): Define ISA without LPM.
 467         (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
 468         Add doc for contraint used in 16 bit lds/sts.
 469         Adjust ISA group for icall, ijmp, pop and push.
 470         Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
 471
 472 2014-05-19  Nick Clifton  <nickc@redhat.com>
 473
 474         * msp430.h (struct msp430_operand_s): Add vshift field.
 475
 476 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 477
 478         * mips.h (INSN_ISA_MASK): Updated.
 479         (INSN_ISA32R3): New define.
 480         (INSN_ISA32R5): New define.
 481         (INSN_ISA64R3): New define.
 482         (INSN_ISA64R5): New define.
 483         (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
 484         INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
 485         (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
 486         mips64r5.
 487         (INSN_UPTO32R3): New define.
 488         (INSN_UPTO32R5): New define.
 489         (INSN_UPTO64R3): New define.
 490         (INSN_UPTO64R5): New define.
 491         (ISA_MIPS32R3): New define.
 492         (ISA_MIPS32R5): New define.
 493         (ISA_MIPS64R3): New define.
 494         (ISA_MIPS64R5): New define.
 495         (CPU_MIPS32R3): New define.
 496         (CPU_MIPS32R5): New define.
 497         (CPU_MIPS64R3): New define.
 498         (CPU_MIPS64R5): New define.
 499
 500 2014-05-01  Richard Sandiford  <rdsandiford@googlemail.com>
 501
 502         * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
 503
 504 2014-04-22  Christian Svensson  <blue@cmd.nu>
 505
 506         * or32.h: Delete.
 507
 508 2014-03-05  Alan Modra  <amodra@gmail.com>
 509
 510         Update copyright years.
 511
 512 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
 513
 514         * mips.h: Updated description of +o, +u, +v and +w for MIPS and
 515         microMIPS.
 516
 517 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 518             Wei-Cheng Wang  <cole945@gmail.com>
 519
 520         * nds32.h: New file for Andes NDS32.
 521
 522 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
 523
 524         * bfin.h: Remove +x file mode.
 525
 526 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 527
 528         * aarch64.h (aarch64_pstatefields): Change element type to
 529         aarch64_sys_reg.
 530
 531 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
 532
 533         * arm.h (ARM_AEXT_V7VE): New define.
 534         (ARM_ARCH_V7VE): New define.
 535         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
 536
 537 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
 538
 539         Revert
 540
 541         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
 542
 543         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
 544         (aarch64_sys_reg_writeonly_p): Ditto.
 545
 546 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
 547
 548         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
 549         (aarch64_sys_reg_writeonly_p): Ditto.
 550
 551 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 552
 553         * aarch64.h (aarch64_sys_reg): New typedef.
 554         (aarch64_sys_regs): Change to define with the new type.
 555         (aarch64_sys_reg_deprecated_p): Declare.
 556
 557 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 558
 559         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
 560         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
 561
 562 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 563
 564         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
 565         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
 566         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 567         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 568         For MIPS, update extension character sequences after +.
 569         (ASE_MSA): New define.
 570         (ASE_MSA64): New define.
 571         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 572         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 573         For microMIPS, update extension character sequences after +.
 574
 575 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 576
 577         PR binutils/15834
 578         * i960.h: Fix typos.
 579
 580 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 581
 582         * mips.h: Remove references to "+I" and imm2_expr.
 583
 584 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 585
 586         * mips.h (M_DEXT, M_DINS): Delete.
 587
 588 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 589
 590         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
 591         (mips_optional_operand_p): New function.
 592
 593 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 594             Richard Sandiford  <rdsandiford@googlemail.com>
 595
 596         * mips.h: Document new VU0 operand characters.
 597         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
 598         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
 599         (OP_REG_R5900_ACC): New mips_reg_operand_types.
 600         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
 601         (mips_vu0_channel_mask): Declare.
 602
 603 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 604
 605         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
 606         (mips_int_operand_min, mips_int_operand_max): New functions.
 607         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
 608
 609 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 610
 611         * mips.h (mips_decode_reg_operand): New function.
 612         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
 613         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
 614         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
 615         New macros.
 616         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
 617         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
 618         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
 619         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
 620         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
 621         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
 622         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
 623         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
 624         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 625         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 626         macros to cover the gaps.
 627         (INSN2_MOD_SP): Replace with...
 628         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 629         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 630         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 631         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 632         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 633         Delete.
 634
 635 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 636
 637         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 638         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 639         (MIPS16_INSN_COND_BRANCH): Delete.
 640
 641 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 642             Kirill Yukhin  <kirill.yukhin@intel.com>
 643             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 644
 645         * i386.h (BND_PREFIX_OPCODE): New.
 646
 647 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 648
 649         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 650         OP_SAVE_RESTORE_LIST.
 651         (decode_mips16_operand): Declare.
 652
 653 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 654
 655         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 656         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 657         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 658         (mips_pcrel_operand): New structures.
 659         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 660         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 661         (decode_mips_operand, decode_micromips_operand): Declare.
 662
 663 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 664
 665         * mips.h: Document MIPS16 "I" opcode.
 666
 667 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 668
 669         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 670         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 671         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 672         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 673         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 674         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 675         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 676         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 677         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 678         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 679         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 680         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 681         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 682         Rename to...
 683         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 684         (M_USD_AB): ...these.
 685
 686 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 687
 688         * mips.h: Remove documentation of "[" and "]".  Update documentation
 689         of "k" and the MDMX formats.
 690
 691 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 692
 693         * mips.h: Update documentation of "+s" and "+S".
 694
 695 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 696
 697         * mips.h: Document "+i".
 698
 699 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 700
 701         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 702         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 703         Delete.
 704         (INSN2_WRITE_GPR_MHI): Rename to...
 705         (INSN2_WRITE_GPR_MH): ...this.
 706
 707 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 708
 709         * mips.h: Remove documentation of "+D" and "+T".
 710
 711 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 712
 713         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 714         Use "source" rather than "destination" for microMIPS "G".
 715
 716 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 717
 718         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 719         values.
 720
 721 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 722
 723         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 724
 725 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 726             Maciej W. Rozycki  <macro@codesourcery.com>
 727             Chao-Ying Fu  <fu@mips.com>
 728
 729         * mips.h (OP_SH_EVAOFFSET): Define.
 730         (OP_MASK_EVAOFFSET): Define.
 731         (INSN_ASE_MASK): Delete.
 732         (ASE_EVA): Define.
 733         (M_CACHEE_AB, M_CACHEE_OB): New.
 734         (M_LBE_OB, M_LBE_AB): New.
 735         (M_LBUE_OB, M_LBUE_AB): New.
 736         (M_LHE_OB, M_LHE_AB): New.
 737         (M_LHUE_OB, M_LHUE_AB): New.
 738         (M_LLE_AB, M_LLE_OB): New.
 739         (M_LWE_OB, M_LWE_AB): New.
 740         (M_LWLE_AB, M_LWLE_OB): New.
 741         (M_LWRE_AB, M_LWRE_OB): New.
 742         (M_PREFE_AB, M_PREFE_OB): New.
 743         (M_SCE_AB, M_SCE_OB): New.
 744         (M_SBE_OB, M_SBE_AB): New.
 745         (M_SHE_OB, M_SHE_AB): New.
 746         (M_SWE_OB, M_SWE_AB): New.
 747         (M_SWLE_AB, M_SWLE_OB): New.
 748         (M_SWRE_AB, M_SWRE_OB): New.
 749         (MICROMIPSOP_SH_EVAOFFSET): Define.
 750         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 751
 752 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 753
 754         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 755
 756 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 757
 758         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 759
 760 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 761
 762         * mips.h (OP_MASK_CODE10): Correct definition.
 763         (OP_SH_CODE10): Likewise.
 764         Add a comment that "+J" is used now for OP_*CODE10.
 765         (INSN_ASE_MASK): Update.
 766         (INSN_VIRT): New macro.
 767         (INSN_VIRT64): New macro
 768
 769 2013-05-02  Nick Clifton  <nickc@redhat.com>
 770
 771         * msp430.h: Add patterns for MSP430X instructions.
 772
 773 2013-04-06  David S. Miller  <davem@davemloft.net>
 774
 775         * sparc.h (F_PREFERRED): Define.
 776         (F_PREF_ALIAS): Define.
 777
 778 2013-04-03  Nick Clifton  <nickc@redhat.com>
 779
 780         * v850.h (V850_INVERSE_PCREL): Define.
 781
 782 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 783
 784         PR binutils/15068
 785         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 786
 787 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 788
 789         PR binutils/15068
 790         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 791         Add 16-bit opcodes.
 792         * tic6xc-opcode-table.h: Add 16-bit insns.
 793         * tic6x.h: Add support for 16-bit insns.
 794
 795 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 796
 797         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 798         and mov.b/w/l Rs,@(d:32,ERd).
 799
 800 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 801
 802         PR gas/15082
 803         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 804         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 805         tic6x_operand_xregpair operand coding type.
 806         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 807         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 808         TIC6X_FLAG_NO_CROSS.
 809
 810 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 811
 812         PR gas/15095
 813         * tic6x.h (enum tic6x_coding_method): Add
 814         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 815         separately the msb and lsb of a register pair.  This is needed to
 816         encode the opcodes in the same way as TI assembler does.
 817         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 818         and rsqrdp opcodes to use the new field coding types.
 819
 820 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 821
 822         * arm.h (CRC_EXT_ARMV8): New constant.
 823         (ARCH_CRC_ARMV8): New macro.
 824
 825 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 826
 827         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 828
 829 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 830             Andrew Jenner <andrew@codesourcery.com>
 831
 832         Based on patches from Altera Corporation.
 833
 834         * nios2.h: New file.
 835
 836 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 837
 838         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 839
 840 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 841
 842         PR gas/15069
 843         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 844
 845 2013-01-24  Nick Clifton  <nickc@redhat.com>
 846
 847         * v850.h: Add e3v5 support.
 848
 849 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 850
 851         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 852
 853 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 854
 855         * ppc.h (PPC_OPCODE_POWER8): New define.
 856         (PPC_OPCODE_HTM): Likewise.
 857
 858 2013-01-10  Will Newton <will.newton@imgtec.com>
 859
 860         * metag.h: New file.
 861
 862 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 863
 864         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 865         (match_opcode): Rename to cr16_match_opcode.
 866
 867 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 868
 869         * mips.h: Add support for r5900 instructions including lq and sq.
 870
 871 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 872
 873         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 874         (make_instruction,match_opcode): Added function prototypes.
 875         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 876
 877 2012-11-23  Alan Modra  <amodra@gmail.com>
 878
 879         * ppc.h (ppc_parse_cpu): Update prototype.
 880
 881 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 882
 883         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 884         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 885
 886 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 887
 888         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 889
 890 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 891
 892         * ia64.h (ia64_opnd): Add new operand types.
 893
 894 2012-08-21  David S. Miller  <davem@davemloft.net>
 895
 896         * sparc.h (F3F4): New macro.
 897
 898 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 899             Laurent Desnogues  <laurent.desnogues@arm.com>
 900             Jim MacArthur  <jim.macarthur@arm.com>
 901             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 902             Nigel Stephens  <nigel.stephens@arm.com>
 903             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 904             Richard Earnshaw  <rearnsha@arm.com>
 905             Sofiane Naci  <sofiane.naci@arm.com>
 906             Tejas Belagod  <tejas.belagod@arm.com>
 907             Yufeng Zhang  <yufeng.zhang@arm.com>
 908
 909         * aarch64.h: New file.
 910
 911 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 912             Maciej W. Rozycki  <macro@codesourcery.com>
 913
 914         * mips.h (mips_opcode): Add the exclusions field.
 915         (OPCODE_IS_MEMBER): Remove macro.
 916         (cpu_is_member): New inline function.
 917         (opcode_is_member): Likewise.
 918
 919 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 920             Catherine Moore  <clm@codesourcery.com>
 921             Maciej W. Rozycki  <macro@codesourcery.com>
 922
 923         * mips.h: Document microMIPS DSP ASE usage.
 924         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 925         microMIPS DSP ASE support.
 926         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 927         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 928         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 929         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 930         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 931         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 932         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 933
 934 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 935
 936         * mips.h: Fix a typo in description.
 937
 938 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 939
 940         * avr.h: (AVR_ISA_XCH): New define.
 941         (AVR_ISA_XMEGA): Use it.
 942         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 943
 944 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 945
 946         * m68hc11.h: Add XGate definitions.
 947         (struct m68hc11_opcode): Add xg_mask field.
 948
 949 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 950             Maciej W. Rozycki  <macro@codesourcery.com>
 951             Rhonda Wittels  <rhonda@codesourcery.com>
 952
 953         * ppc.h (PPC_OPCODE_VLE): New definition.
 954         (PPC_OP_SA): New macro.
 955         (PPC_OP_SE_VLE): New macro.
 956         (PPC_OP): Use a variable shift amount.
 957         (powerpc_operand): Update comments.
 958         (PPC_OPSHIFT_INV): New macro.
 959         (PPC_OPERAND_CR): Replace with...
 960         (PPC_OPERAND_CR_BIT): ...this and
 961         (PPC_OPERAND_CR_REG): ...this.
 962
 963
 964 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 965
 966         * xgate.h: Header file for XGATE assembler.
 967
 968 2012-04-27  David S. Miller  <davem@davemloft.net>
 969
 970         * sparc.h: Document new arg code' )' for crypto RS3
 971         immediates.
 972
 973         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 974         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 975         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 976         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 977         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 978         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 979         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 980         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 981         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 982         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 983         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 984
 985 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 986
 987         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 988
 989 2012-02-27  Alan Modra  <amodra@gmail.com>
 990
 991         * crx.h (cst4_map): Update declaration.
 992
 993 2012-02-25  Walter Lee  <walt@tilera.com>
 994
 995         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 996         TILEGX_OPC_LD_TLS.
 997         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 998         TILEPRO_OPC_LW_TLS_SN.
 999
1000 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
1001
1002         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
1003         (XRELEASE_PREFIX_OPCODE): Likewise.
1004
1005 2011-12-08  Andrew Pinski  <apinski@cavium.com>
1006             Adam Nemet  <anemet@caviumnetworks.com>
1007
1008         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
1009         (INSN_OCTEON2): New macro.
1010         (CPU_OCTEON2): New macro.
1011         (OPCODE_IS_MEMBER): Add Octeon2.
1012
1013 2011-11-29  Andrew Pinski  <apinski@cavium.com>
1014
1015         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
1016         (INSN_OCTEONP): New macro.
1017         (CPU_OCTEONP): New macro.
1018         (OPCODE_IS_MEMBER): Add Octeon+.
1019         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
1020
1021 2011-11-01  DJ Delorie  <dj@redhat.com>
1022
1023         * rl78.h: New file.
1024
1025 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
1026
1027         * mips.h: Fix a typo in description.
1028
1029 2011-09-21  David S. Miller  <davem@davemloft.net>
1030
1031         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
1032         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
1033         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
1034         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
1035
1036 2011-08-09  Chao-ying Fu  <fu@mips.com>
1037             Maciej W. Rozycki  <macro@codesourcery.com>
1038
1039         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
1040         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
1041         (INSN_ASE_MASK): Add the MCU bit.
1042         (INSN_MCU): New macro.
1043         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
1044         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
1045
1046 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
1047
1048         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
1049         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
1050         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
1051         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
1052         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
1053         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
1054         (INSN2_READ_GPR_MMN): Likewise.
1055         (INSN2_READ_FPR_D): Change the bit used.
1056         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
1057         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
1058         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
1059         (INSN2_COND_BRANCH): Likewise.
1060         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
1061         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
1062         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
1063         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
1064         (INSN2_MOD_GPR_MN): Likewise.
1065
1066 2011-08-05  David S. Miller  <davem@davemloft.net>
1067
1068         * sparc.h: Document new format codes '4', '5', and '('.
1069         (OPF_LOW4, RS3): New macros.
1070
1071 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
1072
1073         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
1074         order of flags documented.
1075
1076 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
1077
1078         * mips.h: Clarify the description of microMIPS instruction
1079         manipulation macros.
1080         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
1081
1082 2011-07-24  Chao-ying Fu  <fu@mips.com>
1083             Maciej W. Rozycki  <macro@codesourcery.com>
1084
1085         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
1086         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
1087         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
1088         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
1089         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
1090         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
1091         (OP_MASK_RS3, OP_SH_RS3): Likewise.
1092         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
1093         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1094         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1095         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1096         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1097         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1098         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1099         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1100         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1101         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1102         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1103         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1104         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1105         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1106         (INSN_WRITE_GPR_S): New macro.
1107         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1108         (INSN2_READ_FPR_D): Likewise.
1109         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1110         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1111         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1112         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1113         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1114         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1115         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1116         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1117         (CPU_MICROMIPS): New macro.
1118         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1119         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1120         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1121         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1122         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1123         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1124         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1125         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1126         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1127         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1128         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1129         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1130         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1131         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1132         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1133         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1134         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1135         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1136         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1137         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1138         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1139         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1140         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1141         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1142         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1143         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1144         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1145         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1146         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1147         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1148         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1149         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1150         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1151         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1152         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1153         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1154         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1155         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1156         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1157         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1158         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1159         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1160         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1161         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1162         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1163         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1164         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1165         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1166         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1167         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1168         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1169         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1170         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1171         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1172         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1173         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1174         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1175         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1176         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1177         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1178         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1179         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1180         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1181         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1182         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1183         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1184         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1185         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1186         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1187         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1188         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1189         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1190         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1191         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1192         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1193         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1194         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1195         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1196         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1197         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1198         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1199         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1200         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1201         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1202         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1203         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1204         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1205         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1206         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1207         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1208         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1209         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1210         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1211         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1212         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1213         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1214         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1215         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1216         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1217         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1218         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1219         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1220         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1221         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1222         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1223         (micromips_opcodes): New declaration.
1224         (bfd_micromips_num_opcodes): Likewise.
1225
1226 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
1227
1228         * mips.h (INSN_TRAP): Rename to...
1229         (INSN_NO_DELAY_SLOT): ... this.
1230         (INSN_SYNC): Remove macro.
1231
1232 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
1233
1234         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1235         a duplicate of AVR_ISA_SPM.
1236
1237 2011-07-01  Nick Clifton  <nickc@redhat.com>
1238
1239         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1240
1241 2011-06-18  Robin Getz  <robin.getz@analog.com>
1242
1243         * bfin.h (is_macmod_signed): New func
1244
1245 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
1246
1247         * bfin.h (is_macmod_pmove): Add missing space before func args.
1248         (is_macmod_hmove): Likewise.
1249
1250 2011-06-13  Walter Lee  <walt@tilera.com>
1251
1252         * tilegx.h: New file.
1253         * tilepro.h: New file.
1254
1255 2011-05-31  Paul Brook  <paul@codesourcery.com>
1256
1257         * arm.h (ARM_ARCH_V7R_IDIV): Define.
1258
1259 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
1260
1261         * s390.h: Replace S390_OPERAND_REG_EVEN with
1262         S390_OPERAND_REG_PAIR.
1263
1264 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
1265
1266         * s390.h: Add S390_OPCODE_REG_EVEN flag.
1267
1268 2011-04-18  Julian Brown  <julian@codesourcery.com>
1269
1270         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1271
1272 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
1273
1274         PR gas/12296
1275         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1276
1277 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
1278
1279         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1280         New instruction set flags.
1281         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1282
1283 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
1284
1285         * mips.h (M_PREF_AB): New enum value.
1286
1287 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
1288
1289         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1290         M_IU): Define.
1291         (is_macmod_pmove, is_macmod_hmove): New functions.
1292
1293 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
1294
1295         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1296
1297 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
1298
1299         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1300         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1301
1302 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1303
1304         PR gas/11395
1305         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
1306         "bb" entries.
1307
1308 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1309
1310         PR gas/11395
1311         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1312
1313 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
1314
1315         * mips.h: Update commentary after last commit.
1316
1317 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
1318
1319         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1320         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1321         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1322
1323 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
1324
1325         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1326
1327 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
1328
1329         * mips.h: Fix previous commit.
1330
1331 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
1332
1333         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1334         (INSN_LOONGSON_3A): Clear bit 31.
1335
1336 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
1337
1338         PR gas/12198
1339         * arm.h (ARM_AEXT_V6M_ONLY): New define.
1340         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1341         (ARM_ARCH_V6M_ONLY): New define.
1342
1343 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
1344
1345         * mips.h (INSN_LOONGSON_3A): Defined.
1346         (CPU_LOONGSON_3A): Defined.
1347         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1348
1349 2010-10-09  Matt Rice  <ratmice@gmail.com>
1350
1351         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1352         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1353
1354 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
1355
1356         * arm.h (ARM_EXT_VIRT): New define.
1357         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1358         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1359         Extensions.
1360
1361 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
1362
1363         * arm.h (ARM_AEXT_ADIV): New define.
1364         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1365
1366 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
1367
1368         * arm.h (ARM_EXT_OS): New define.
1369         (ARM_AEXT_V6SM): Likewise.
1370         (ARM_ARCH_V6SM): Likewise.
1371
1372 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
1373
1374         * arm.h (ARM_EXT_MP): Add.
1375         (ARM_ARCH_V7A_MP): Likewise.
1376
1377 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
1378
1379         * bfin.h: Declare pseudoChr structs/defines.
1380
1381 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
1382
1383         * bfin.h: Strip trailing whitespace.
1384
1385 2010-07-29  DJ Delorie  <dj@redhat.com>
1386
1387         * rx.h (RX_Operand_Type): Add TwoReg.
1388         (RX_Opcode_ID): Remove ediv and ediv2.
1389
1390 2010-07-27  DJ Delorie  <dj@redhat.com>
1391
1392         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1393
1394 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
1395             Ina Pandit  <ina.pandit@kpitcummins.com>
1396
1397         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1398         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1399         PROCESSOR_V850E2_ALL.
1400         Remove PROCESSOR_V850EA support.
1401         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1402         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1403         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1404         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1405         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1406         V850_OPERAND_PERCENT.
1407         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1408         V850_NOT_R0.
1409         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1410         and V850E_PUSH_POP
1411
1412 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
1413
1414         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1415         (MIPS16_INSN_BRANCH): Rename to...
1416         (MIPS16_INSN_COND_BRANCH): ... this.
1417
1418 2010-07-03  Alan Modra  <amodra@gmail.com>
1419
1420         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1421         Renumber other PPC_OPCODE defines.
1422
1423 2010-07-03  Alan Modra  <amodra@gmail.com>
1424
1425         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1426
1427 2010-06-29  Alan Modra  <amodra@gmail.com>
1428
1429         * maxq.h: Delete file.
1430
1431 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
1432
1433         * ppc.h (PPC_OPCODE_E500): Define.
1434
1435 2010-05-26  Catherine Moore  <clm@codesourcery.com>
1436
1437         * opcode/mips.h (INSN_MIPS16): Remove.
1438
1439 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
1440
1441         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1442
1443 2010-04-15  Nick Clifton  <nickc@redhat.com>
1444
1445         * alpha.h: Update copyright notice to use GPLv3.
1446         * arc.h: Likewise.
1447         * arm.h: Likewise.
1448         * avr.h: Likewise.
1449         * bfin.h: Likewise.
1450         * cgen.h: Likewise.
1451         * convex.h: Likewise.
1452         * cr16.h: Likewise.
1453         * cris.h: Likewise.
1454         * crx.h: Likewise.
1455         * d10v.h: Likewise.
1456         * d30v.h: Likewise.
1457         * dlx.h: Likewise.
1458         * h8300.h: Likewise.
1459         * hppa.h: Likewise.
1460         * i370.h: Likewise.
1461         * i386.h: Likewise.
1462         * i860.h: Likewise.
1463         * i960.h: Likewise.
1464         * ia64.h: Likewise.
1465         * m68hc11.h: Likewise.
1466         * m68k.h: Likewise.
1467         * m88k.h: Likewise.
1468         * maxq.h: Likewise.
1469         * mips.h: Likewise.
1470         * mmix.h: Likewise.
1471         * mn10200.h: Likewise.
1472         * mn10300.h: Likewise.
1473         * msp430.h: Likewise.
1474         * np1.h: Likewise.
1475         * ns32k.h: Likewise.
1476         * or32.h: Likewise.
1477         * pdp11.h: Likewise.
1478         * pj.h: Likewise.
1479         * pn.h: Likewise.
1480         * ppc.h: Likewise.
1481         * pyr.h: Likewise.
1482         * rx.h: Likewise.
1483         * s390.h: Likewise.
1484         * score-datadep.h: Likewise.
1485         * score-inst.h: Likewise.
1486         * sparc.h: Likewise.
1487         * spu-insns.h: Likewise.
1488         * spu.h: Likewise.
1489         * tic30.h: Likewise.
1490         * tic4x.h: Likewise.
1491         * tic54x.h: Likewise.
1492         * tic80.h: Likewise.
1493         * v850.h: Likewise.
1494         * vax.h: Likewise.
1495
1496 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
1497
1498         * tic6x-control-registers.h, tic6x-insn-formats.h,
1499         tic6x-opcode-table.h, tic6x.h: New.
1500
1501 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
1502
1503         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1504
1505 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
1506
1507         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1508
1509 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
1510
1511         * ia64.h (ia64_find_opcode): Remove argument name.
1512         (ia64_find_next_opcode): Likewise.
1513         (ia64_dis_opcode): Likewise.
1514         (ia64_free_opcode): Likewise.
1515         (ia64_find_dependency): Likewise.
1516
1517 2009-11-22  Doug Evans  <dje@sebabeach.org>
1518
1519         * cgen.h: Include bfd_stdint.h.
1520         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1521
1522 2009-11-18  Paul Brook  <paul@codesourcery.com>
1523
1524         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1525
1526 2009-11-17  Paul Brook  <paul@codesourcery.com>
1527         Daniel Jacobowitz  <dan@codesourcery.com>
1528
1529         * arm.h (ARM_EXT_V6_DSP): Define.
1530         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1531         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1532
1533 2009-11-04  DJ Delorie  <dj@redhat.com>
1534
1535         * rx.h (rx_decode_opcode) (mvtipl): Add.
1536         (mvtcp, mvfcp, opecp): Remove.
1537
1538 2009-11-02  Paul Brook  <paul@codesourcery.com>
1539
1540         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1541         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1542         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1543         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1544         FPU_ARCH_NEON_VFP_V4): Define.
1545
1546 2009-10-23  Doug Evans  <dje@sebabeach.org>
1547
1548         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1549         * cgen.h: Update.  Improve multi-inclusion macro name.
1550
1551 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1552
1553         * ppc.h (PPC_OPCODE_476): Define.
1554
1555 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1556
1557         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1558
1559 2009-09-29  DJ Delorie  <dj@redhat.com>
1560
1561         * rx.h: New file.
1562
1563 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1564
1565         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1566
1567 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1568
1569         * ppc.h (PPC_OPCODE_PPCA2): New.
1570
1571 2009-09-05  Martin Thuresson  <martin@mtme.org>
1572
1573         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1574
1575 2009-08-29  Martin Thuresson  <martin@mtme.org>
1576
1577         * tic30.h (template): Rename type template to
1578         insn_template. Updated code to use new name.
1579         * tic54x.h (template): Rename type template to
1580         insn_template.
1581
1582 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1583
1584         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1585
1586 2009-06-11  Anthony Green  <green@moxielogic.com>
1587
1588         * moxie.h (MOXIE_F3_PCREL): Define.
1589         (moxie_form3_opc_info): Grow.
1590
1591 2009-06-06  Anthony Green  <green@moxielogic.com>
1592
1593         * moxie.h (MOXIE_F1_M): Define.
1594
1595 2009-04-15  Anthony Green  <green@moxielogic.com>
1596
1597         * moxie.h: Created.
1598
1599 2009-04-06  DJ Delorie  <dj@redhat.com>
1600
1601         * h8300.h: Add relaxation attributes to MOVA opcodes.
1602
1603 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1604
1605         * ppc.h (ppc_parse_cpu): Declare.
1606
1607 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1608
1609         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1610         and _IMM11 for mbitclr and mbitset.
1611         * score-datadep.h: Update dependency information.
1612
1613 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1614
1615         * ppc.h (PPC_OPCODE_POWER7): New.
1616
1617 2009-02-06  Doug Evans  <dje@google.com>
1618
1619         * i386.h: Add comment regarding sse* insns and prefixes.
1620
1621 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1622
1623         * mips.h (INSN_XLR): Define.
1624         (INSN_CHIP_MASK): Update.
1625         (CPU_XLR): Define.
1626         (OPCODE_IS_MEMBER): Update.
1627         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1628
1629 2009-01-28  Doug Evans  <dje@google.com>
1630
1631         * opcode/i386.h: Add multiple inclusion protection.
1632         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1633         (EDI_REG_NUM): New macros.
1634         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1635         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1636         (REX_PREFIX_P): New macro.
1637
1638 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1639
1640         * ppc.h (struct powerpc_opcode): New field "deprecated".
1641         (PPC_OPCODE_NOPOWER4): Delete.
1642
1643 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1644
1645         * mips.h: Define CPU_R14000, CPU_R16000.
1646         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1647
1648 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1649
1650         * arm.h (FPU_NEON_FP16): New.
1651         (FPU_ARCH_NEON_FP16): New.
1652
1653 2008-11-06  Chao-ying Fu  <fu@mips.com>
1654
1655         * mips.h: Doucument '1' for 5-bit sync type.
1656
1657 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1658
1659         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1660         IA64_RS_CR.
1661
1662 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1663
1664         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1665
1666 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1667
1668         * ppc.h (PPC_OPCODE_405): Define.
1669         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1670
1671 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1672
1673         * ppc.h (ppc_cpu_t): New typedef.
1674         (struct powerpc_opcode <flags>): Use it.
1675         (struct powerpc_operand <insert, extract>): Likewise.
1676         (struct powerpc_macro <flags>): Likewise.
1677
1678 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1679
1680         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1681         Update comment before MIPS16 field descriptors to mention MIPS16.
1682         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1683         BBIT.
1684         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1685         New bit masks and shift counts for cins and exts.
1686
1687         * mips.h: Document new field descriptors +Q.
1688         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1689
1690 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1691
1692         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1693         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1694
1695 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1696
1697         * ppc.h: (PPC_OPCODE_E500MC): New.
1698
1699 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1700
1701         * i386.h (MAX_OPERANDS): Set to 5.
1702         (MAX_MNEM_SIZE): Changed to 20.
1703
1704 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1705
1706         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1707
1708 2008-03-09  Paul Brook  <paul@codesourcery.com>
1709
1710         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1711
1712 2008-03-04  Paul Brook  <paul@codesourcery.com>
1713
1714         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1715         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1716         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1717
1718 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1719             Nick Clifton  <nickc@redhat.com>
1720
1721         PR 3134
1722         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1723         with a 32-bit displacement but without the top bit of the 4th byte
1724         set.
1725
1726 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1727
1728         * cr16.h (cr16_num_optab): Declared.
1729
1730 2008-02-14  Hakan Ardo  <hakan@debian.org>
1731
1732         PR gas/2626
1733         * avr.h (AVR_ISA_2xxe): Define.
1734
1735 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1736
1737         * mips.h: Update copyright.
1738         (INSN_CHIP_MASK): New macro.
1739         (INSN_OCTEON): New macro.
1740         (CPU_OCTEON): New macro.
1741         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1742
1743 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1744
1745         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1746
1747 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1748
1749         * avr.h (AVR_ISA_USB162): Add new opcode set.
1750         (AVR_ISA_AVR3): Likewise.
1751
1752 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1753
1754         * mips.h (INSN_LOONGSON_2E): New.
1755         (INSN_LOONGSON_2F): New.
1756         (CPU_LOONGSON_2E): New.
1757         (CPU_LOONGSON_2F): New.
1758         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1759
1760 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1761
1762         * mips.h (INSN_ISA*): Redefine certain values as an
1763         enumeration.  Update comments.
1764         (mips_isa_table): New.
1765         (ISA_MIPS*): Redefine to match enumeration.
1766         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1767         values.
1768
1769 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1770
1771         * ppc.h (PPC_OPCODE_PPCPS): New.
1772
1773 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1774
1775         * m68k.h: Document j K & E.
1776
1777 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1778
1779         * cr16.h: New file for CR16 target.
1780
1781 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1782
1783         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1784
1785 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1786
1787         * m68k.h (mcfisa_c): New.
1788         (mcfusp, mcf_mask): Adjust.
1789
1790 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1791
1792         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1793         (num_powerpc_operands): Declare.
1794         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1795         (PPC_OPERAND_PLUS1): Define.
1796
1797 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1798
1799         * i386.h (REX_MODE64): Renamed to ...
1800         (REX_W): This.
1801         (REX_EXTX): Renamed to ...
1802         (REX_R): This.
1803         (REX_EXTY): Renamed to ...
1804         (REX_X): This.
1805         (REX_EXTZ): Renamed to ...
1806         (REX_B): This.
1807
1808 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1809
1810         * i386.h: Add entries from config/tc-i386.h and move tables
1811         to opcodes/i386-opc.h.
1812
1813 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1814
1815         * i386.h (FloatDR): Removed.
1816         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1817
1818 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1819
1820         * spu-insns.h: Add soma double-float insns.
1821
1822 2007-02-20  Thiemo Seufer  <ths@mips.com>
1823             Chao-Ying Fu  <fu@mips.com>
1824
1825         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1826         (INSN_DSPR2): Add flag for DSP R2 instructions.
1827         (M_BALIGN): New macro.
1828
1829 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1830
1831         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1832         and Seg3ShortFrom with Shortform.
1833
1834 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1835
1836         PR gas/4027
1837         * i386.h (i386_optab): Put the real "test" before the pseudo
1838         one.
1839
1840 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1841
1842         * m68k.h (m68010up): OR fido_a.
1843
1844 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1845
1846         * m68k.h (fido_a): New.
1847
1848 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1849
1850         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1851         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1852         values.
1853
1854 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1855
1856         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1857
1858 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1859
1860         * score-inst.h (enum score_insn_type): Add Insn_internal.
1861
1862 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1863             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1864             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1865             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1866             Alan Modra  <amodra@bigpond.net.au>
1867
1868         * spu-insns.h: New file.
1869         * spu.h: New file.
1870
1871 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1872
1873         * ppc.h (PPC_OPCODE_CELL): Define.
1874
1875 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1876
1877         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1878         in amdfam10 architecture.
1879
1880 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1881
1882         * i386.h: Replace CpuMNI with CpuSSSE3.
1883
1884 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1885             Joseph Myers  <joseph@codesourcery.com>
1886             Ian Lance Taylor  <ian@wasabisystems.com>
1887             Ben Elliston  <bje@wasabisystems.com>
1888
1889         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1890
1891 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1892
1893         * score-datadep.h: New file.
1894         * score-inst.h: New file.
1895
1896 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1897
1898         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1899         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1900         movdq2q and movq2dq.
1901
1902 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1903            Michael Meissner             <michael.meissner@amd.com>
1904
1905         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1906
1907 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1908
1909         * i386.h (i386_optab): Add "nop" with memory reference.
1910
1911 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1912
1913         * i386.h (i386_optab): Update comment for 64bit NOP.
1914
1915 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1916             Anton Blanchard  <anton@samba.org>
1917
1918         * ppc.h (PPC_OPCODE_POWER6): Define.
1919         Adjust whitespace.
1920
1921 2006-06-05  Thiemo Seufer  <ths@mips.com>
1922
1923         * mips.h: Improve description of MT flags.
1924
1925 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1926
1927         * m68k.h (mcf_mask): Define.
1928
1929 2006-05-05  Thiemo Seufer  <ths@mips.com>
1930             David Ung  <davidu@mips.com>
1931
1932         * mips.h (enum): Add macro M_CACHE_AB.
1933
1934 2006-05-04  Thiemo Seufer  <ths@mips.com>
1935             Nigel Stephens  <nigel@mips.com>
1936             David Ung  <davidu@mips.com>
1937
1938         * mips.h: Add INSN_SMARTMIPS define.
1939
1940 2006-04-30  Thiemo Seufer  <ths@mips.com>
1941             David Ung  <davidu@mips.com>
1942
1943         * mips.h: Defines udi bits and masks.  Add description of
1944         characters which may appear in the args field of udi
1945         instructions.
1946
1947 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1948
1949         * mips.h: Improve comments describing the bitfield instruction
1950         fields.
1951
1952 2006-04-26  Julian Brown  <julian@codesourcery.com>
1953
1954         * arm.h (FPU_VFP_EXT_V3): Define constant.
1955         (FPU_NEON_EXT_V1): Likewise.
1956         (FPU_VFP_HARD): Update.
1957         (FPU_VFP_V3): Define macro.
1958         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1959
1960 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1961
1962         * avr.h (AVR_ISA_PWMx): New.
1963
1964 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1965
1966         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1967         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1968         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1969         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1970         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1971
1972 2006-03-10  Paul Brook  <paul@codesourcery.com>
1973
1974         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1975
1976 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1977
1978         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1979         first.  Correct mask of bb "B" opcode.
1980
1981 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1982
1983         * i386.h (i386_optab): Support Intel Merom New Instructions.
1984
1985 2006-02-24  Paul Brook  <paul@codesourcery.com>
1986
1987         * arm.h: Add V7 feature bits.
1988
1989 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1990
1991         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1992
1993 2006-01-31  Paul Brook  <paul@codesourcery.com>
1994         Richard Earnshaw <rearnsha@arm.com>
1995
1996         * arm.h: Use ARM_CPU_FEATURE.
1997         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1998         (arm_feature_set): Change to a structure.
1999         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
2000         ARM_FEATURE): New macros.
2001
2002 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
2003
2004         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
2005         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
2006         (ADD_PC_INCR_OPCODE): Don't define.
2007
2008 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
2009
2010         PR gas/1874
2011         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
2012
2013 2005-11-14  David Ung  <davidu@mips.com>
2014
2015         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
2016         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
2017         save/restore encoding of the args field.
2018
2019 2005-10-28  Dave Brolley  <brolley@redhat.com>
2020
2021         Contribute the following changes:
2022         2005-02-16  Dave Brolley  <brolley@redhat.com>
2023
2024         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
2025         cgen_isa_mask_* to cgen_bitset_*.
2026         * cgen.h: Likewise.
2027
2028         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
2029
2030         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
2031         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
2032         (CGEN_CPU_TABLE): Make isas a ponter.
2033
2034         2003-09-29  Dave Brolley  <brolley@redhat.com>
2035
2036         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
2037         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
2038         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
2039
2040         2002-12-13  Dave Brolley  <brolley@redhat.com>
2041
2042         * cgen.h (symcat.h): #include it.
2043         (cgen-bitset.h): #include it.
2044         (CGEN_ATTR_VALUE_TYPE): Now a union.
2045         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
2046         (CGEN_ATTR_ENTRY): 'value' now unsigned.
2047         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
2048         * cgen-bitset.h: New file.
2049
2050 2005-09-30  Catherine Moore  <clm@cm00re.com>
2051
2052         * bfin.h: New file.
2053
2054 2005-10-24  Jan Beulich  <jbeulich@novell.com>
2055
2056         * ia64.h (enum ia64_opnd): Move memory operand out of set of
2057         indirect operands.
2058
2059 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2060
2061         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
2062         Add FLAG_STRICT to pa10 ftest opcode.
2063
2064 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2065
2066         * hppa.h (pa_opcodes): Remove lha entries.
2067
2068 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2069
2070         * hppa.h (FLAG_STRICT): Revise comment.
2071         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
2072         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
2073         entries for "fdc".
2074
2075 2005-09-30  Catherine Moore  <clm@cm00re.com>
2076
2077         * bfin.h: New file.
2078
2079 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2080
2081         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
2082
2083 2005-09-06  Chao-ying Fu  <fu@mips.com>
2084
2085         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
2086         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
2087         define.
2088         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
2089         (INSN_ASE_MASK): Update to include INSN_MT.
2090         (INSN_MT): New define for MT ASE.
2091
2092 2005-08-25  Chao-ying Fu  <fu@mips.com>
2093
2094         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2095         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2096         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2097         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2098         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2099         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2100         instructions.
2101         (INSN_DSP): New define for DSP ASE.
2102
2103 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
2104
2105         * a29k.h: Delete.
2106
2107 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
2108
2109         * ppc.h (PPC_OPCODE_E300): Define.
2110
2111 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
2112
2113         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2114
2115 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2116
2117         PR gas/336
2118         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2119         and pitlb.
2120
2121 2005-07-27  Jan Beulich  <jbeulich@novell.com>
2122
2123         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2124         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2125         Add movq-s as 64-bit variants of movd-s.
2126
2127 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2128
2129         * hppa.h: Fix punctuation in comment.
2130
2131         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
2132         implicit space-register addressing.  Set space-register bits on opcodes
2133         using implicit space-register addressing.  Add various missing pa20
2134         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
2135         space-register addressing.  Use "fE" instead of "fe" in various
2136         fstw opcodes.
2137
2138 2005-07-18  Jan Beulich  <jbeulich@novell.com>
2139
2140         * i386.h (i386_optab): Operands of aam and aad are unsigned.
2141
2142 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
2143
2144         * i386.h (i386_optab): Support Intel VMX Instructions.
2145
2146 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2147
2148         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2149
2150 2005-07-05  Jan Beulich  <jbeulich@novell.com>
2151
2152         * i386.h (i386_optab): Add new insns.
2153
2154 2005-07-01  Nick Clifton  <nickc@redhat.com>
2155
2156         * sparc.h: Add typedefs to structure declarations.
2157
2158 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
2159
2160         PR 1013
2161         * i386.h (i386_optab): Update comments for 64bit addressing on
2162         mov. Allow 64bit addressing for mov and movq.
2163
2164 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2165
2166         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2167         respectively, in various floating-point load and store patterns.
2168
2169 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
2170
2171         * hppa.h (FLAG_STRICT): Correct comment.
2172         (pa_opcodes): Update load and store entries to allow both PA 1.X and
2173         PA 2.0 mneumonics when equivalent.  Entries with cache control
2174         completers now require PA 1.1.  Adjust whitespace.
2175
2176 2005-05-19  Anton Blanchard  <anton@samba.org>
2177
2178         * ppc.h (PPC_OPCODE_POWER5): Define.
2179
2180 2005-05-10  Nick Clifton  <nickc@redhat.com>
2181
2182         * Update the address and phone number of the FSF organization in
2183         the GPL notices in the following files:
2184         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2185         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2186         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2187         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2188         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2189         tic54x.h, tic80.h, v850.h, vax.h
2190
2191 2005-05-09  Jan Beulich  <jbeulich@novell.com>
2192
2193         * i386.h (i386_optab): Add ht and hnt.
2194
2195 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
2196
2197         * i386.h: Insert hyphens into selected VIA PadLock extensions.
2198         Add xcrypt-ctr.  Provide aliases without hyphens.
2199
2200 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
2201
2202         Moved from ../ChangeLog
2203
2204         2005-04-12  Paul Brook  <paul@codesourcery.com>
2205         * m88k.h: Rename psr macros to avoid conflicts.
2206
2207         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
2208         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2209         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2210         and ARM_ARCH_V6ZKT2.
2211
2212         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
2213         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2214         Remove redundant instruction types.
2215         (struct argument): X_op - new field.
2216         (struct cst4_entry): Remove.
2217         (no_op_insn): Declare.
2218
2219         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
2220         * crx.h (enum argtype): Rename types, remove unused types.
2221
2222         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
2223         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2224         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2225         (enum operand_type): Rearrange operands, edit comments.
2226         replace us<N> with ui<N> for unsigned immediate.
2227         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2228         displacements (respectively).
2229         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2230         (instruction type): Add NO_TYPE_INS.
2231         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2232         (operand_entry): New field - 'flags'.
2233         (operand flags): New.
2234
2235         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
2236         * crx.h (operand_type): Remove redundant types i3, i4,
2237         i5, i8, i12.
2238         Add new unsigned immediate types us3, us4, us5, us16.
2239
2240 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
2241
2242         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2243         adjust them accordingly.
2244
2245 2005-04-01  Jan Beulich  <jbeulich@novell.com>
2246
2247         * i386.h (i386_optab): Add rdtscp.
2248
2249 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
2250
2251         * i386.h (i386_optab): Don't allow the `l' suffix for moving
2252         between memory and segment register. Allow movq for moving between
2253         general-purpose register and segment register.
2254
2255 2005-02-09  Jan Beulich  <jbeulich@novell.com>
2256
2257         PR gas/707
2258         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2259         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2260         fnstsw.
2261
2262 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
2263
2264         * m68k.h (m68008, m68ec030, m68882): Remove.
2265         (m68k_mask): New.
2266         (cpu_m68k, cpu_cf): New.
2267         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2268         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2269
2270 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
2271
2272         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
2273         * cgen.h (enum cgen_parse_operand_type): Add
2274         CGEN_PARSE_OPERAND_SYMBOLIC.
2275
2276 2005-01-21  Fred Fish  <fnf@specifixinc.com>
2277
2278         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2279         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2280         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2281
2282 2005-01-19  Fred Fish  <fnf@specifixinc.com>
2283
2284         * mips.h (struct mips_opcode): Add new pinfo2 member.
2285         (INSN_ALIAS): New define for opcode table entries that are
2286         specific instances of another entry, such as 'move' for an 'or'
2287         with a zero operand.
2288         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2289         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2290
2291 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
2292
2293         * mips.h (CPU_RM9000): Define.
2294         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2295
2296 2004-11-25 Jan Beulich  <jbeulich@novell.com>
2297
2298         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2299         to/from test registers are illegal in 64-bit mode. Add missing
2300         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2301         (previously one had to explicitly encode a rex64 prefix). Re-enable
2302         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2303         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2304
2305 2004-11-23 Jan Beulich  <jbeulich@novell.com>
2306
2307         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2308         available only with SSE2. Change the MMX additions introduced by SSE
2309         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2310         instructions by their now designated identifier (since combining i686
2311         and 3DNow! does not really imply 3DNow!A).
2312
2313 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
2314
2315         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2316         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2317
2318 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
2319             Vineet Sharma      <vineets@noida.hcltech.com>
2320
2321         * maxq.h: New file: Disassembly information for the maxq port.
2322
2323 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
2324
2325         * i386.h (i386_optab): Put back "movzb".
2326
2327 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
2328
2329         * cris.h (enum cris_insn_version_usage): Tweak formatting and
2330         comments.  Remove member cris_ver_sim.  Add members
2331         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2332         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2333         (struct cris_support_reg, struct cris_cond15): New types.
2334         (cris_conds15): Declare.
2335         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2336         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2337         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2338         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2339         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2340         SIZE_FIELD_UNSIGNED.
2341
2342 2004-11-04 Jan Beulich  <jbeulich@novell.com>
2343
2344         * i386.h (sldx_Suf): Remove.
2345         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2346         (q_FP): Define, implying no REX64.
2347         (x_FP, sl_FP): Imply FloatMF.
2348         (i386_optab): Split reg and mem forms of moving from segment registers
2349         so that the memory forms can ignore the 16-/32-bit operand size
2350         distinction. Adjust a few others for Intel mode. Remove *FP uses from
2351         all non-floating-point instructions. Unite 32- and 64-bit forms of
2352         movsx, movzx, and movd. Adjust floating point operations for the above
2353         changes to the *FP macros. Add DefaultSize to floating point control
2354         insns operating on larger memory ranges. Remove left over comments
2355         hinting at certain insns being Intel-syntax ones where the ones
2356         actually meant are already gone.
2357
2358 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
2359
2360         * crx.h: Add COPS_REG_INS - Coprocessor Special register
2361         instruction type.
2362
2363 2004-09-30  Paul Brook  <paul@codesourcery.com>
2364
2365         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2366         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2367
2368 2004-09-11  Theodore A. Roth  <troth@openavr.org>
2369
2370         * avr.h: Add support for
2371         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2372
2373 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
2374
2375         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2376
2377 2004-08-24  Dmitry Diky  <diwil@spec.ru>
2378
2379         * msp430.h (msp430_opc): Add new instructions.
2380         (msp430_rcodes): Declare new instructions.
2381         (msp430_hcodes): Likewise..
2382
2383 2004-08-13  Nick Clifton  <nickc@redhat.com>
2384
2385         PR/301
2386         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2387         processors.
2388
2389 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
2390
2391         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2392
2393 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
2394
2395         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2396
2397 2004-07-21  Jan Beulich  <jbeulich@novell.com>
2398
2399         * i386.h: Adjust instruction descriptions to better match the
2400         specification.
2401
2402 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
2403
2404         * arm.h: Remove all old content.  Replace with architecture defines
2405         from gas/config/tc-arm.c.
2406
2407 2004-07-09  Andreas Schwab  <schwab@suse.de>
2408
2409         * m68k.h: Fix comment.
2410
2411 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
2412
2413         * crx.h: New file.
2414
2415 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
2416
2417         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2418
2419 2004-05-24  Peter Barada  <peter@the-baradas.com>
2420
2421         * m68k.h: Add 'size' to m68k_opcode.
2422
2423 2004-05-05  Peter Barada  <peter@the-baradas.com>
2424
2425         * m68k.h: Switch from ColdFire chip name to core variant.
2426
2427 2004-04-22  Peter Barada  <peter@the-baradas.com>
2428
2429         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
2430         descriptions for new EMAC cases.
2431         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2432         handle Motorola MAC syntax.
2433         Allow disassembly of ColdFire V4e object files.
2434
2435 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
2436
2437         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
2438
2439 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
2440
2441         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2442
2443 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
2444
2445         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2446
2447 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
2448
2449         * i386.h (i386_optab): Added xstore/xcrypt insns.
2450
2451 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2452
2453         * h8300.h (32bit ldc/stc): Add relaxing support.
2454
2455 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
2456
2457         * h8300.h (BITOP): Pass MEMRELAX flag.
2458
2459 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2460
2461         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2462         except for the H8S.
2463
2464 For older changes see ChangeLog-9103
2465 \f
2466 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2467
2468 Copying and distribution of this file, with or without modification,
2469 are permitted in any medium without royalty provided the copyright
2470 notice and this notice are preserved.
2471
2472 Local Variables:
2473 mode: change-log
2474 left-margin: 8
2475 fill-column: 74
2476 version-control: never
2477 End: