include/opcode/ChangeLog

   1 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips.h: Remove documentation of "+D" and "+T".
   4
   5 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
   6
   7         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
   8         Use "source" rather than "destination" for microMIPS "G".
   9
  10 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  11
  12         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
  13         values.
  14
  15 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
  16
  17         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
  18
  19 2013-06-17  Catherine Moore  <clm@codesourcery.com>
  20             Maciej W. Rozycki  <macro@codesourcery.com>
  21             Chao-Ying Fu  <fu@mips.com>
  22
  23         * mips.h (OP_SH_EVAOFFSET): Define.
  24         (OP_MASK_EVAOFFSET): Define.
  25         (INSN_ASE_MASK): Delete.
  26         (ASE_EVA): Define.
  27         (M_CACHEE_AB, M_CACHEE_OB): New.
  28         (M_LBE_OB, M_LBE_AB): New.
  29         (M_LBUE_OB, M_LBUE_AB): New.
  30         (M_LHE_OB, M_LHE_AB): New.
  31         (M_LHUE_OB, M_LHUE_AB): New.
  32         (M_LLE_AB, M_LLE_OB): New.
  33         (M_LWE_OB, M_LWE_AB): New.
  34         (M_LWLE_AB, M_LWLE_OB): New.
  35         (M_LWRE_AB, M_LWRE_OB): New.
  36         (M_PREFE_AB, M_PREFE_OB): New.
  37         (M_SCE_AB, M_SCE_OB): New.
  38         (M_SBE_OB, M_SBE_AB): New.
  39         (M_SHE_OB, M_SHE_AB): New.
  40         (M_SWE_OB, M_SWE_AB): New.
  41         (M_SWLE_AB, M_SWLE_OB): New.
  42         (M_SWRE_AB, M_SWRE_OB): New.
  43         (MICROMIPSOP_SH_EVAOFFSET): Define.
  44         (MICROMIPSOP_MASK_EVAOFFSET): Define.
  45
  46 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
  47
  48         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
  49
  50 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
  51
  52         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
  53
  54 2013-05-09  Andrew Pinski  <apinski@cavium.com>
  55
  56         * mips.h (OP_MASK_CODE10): Correct definition.
  57         (OP_SH_CODE10): Likewise.
  58         Add a comment that "+J" is used now for OP_*CODE10.
  59         (INSN_ASE_MASK): Update.
  60         (INSN_VIRT): New macro.
  61         (INSN_VIRT64): New macro
  62
  63 2013-05-02  Nick Clifton  <nickc@redhat.com>
  64
  65         * msp430.h: Add patterns for MSP430X instructions.
  66
  67 2013-04-06  David S. Miller  <davem@davemloft.net>
  68
  69         * sparc.h (F_PREFERRED): Define.
  70         (F_PREF_ALIAS): Define.
  71
  72 2013-04-03  Nick Clifton  <nickc@redhat.com>
  73
  74         * v850.h (V850_INVERSE_PCREL): Define.
  75
  76 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  77
  78         PR binutils/15068
  79         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
  80
  81 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  82
  83         PR binutils/15068
  84         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
  85         Add 16-bit opcodes.
  86         * tic6xc-opcode-table.h: Add 16-bit insns.
  87         * tic6x.h: Add support for 16-bit insns.
  88
  89 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
  90
  91         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
  92         and mov.b/w/l Rs,@(d:32,ERd).
  93
  94 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
  95
  96         PR gas/15082
  97         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
  98         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
  99         tic6x_operand_xregpair operand coding type.
 100         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 101         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 102         TIC6X_FLAG_NO_CROSS.
 103
 104 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 105
 106         PR gas/15095
 107         * tic6x.h (enum tic6x_coding_method): Add
 108         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 109         separately the msb and lsb of a register pair.  This is needed to
 110         encode the opcodes in the same way as TI assembler does.
 111         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 112         and rsqrdp opcodes to use the new field coding types.
 113
 114 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 115
 116         * arm.h (CRC_EXT_ARMV8): New constant.
 117         (ARCH_CRC_ARMV8): New macro.
 118
 119 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 120
 121         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 122
 123 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 124             Andrew Jenner <andrew@codesourcery.com>
 125
 126         Based on patches from Altera Corporation.
 127
 128         * nios2.h: New file.
 129
 130 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 131
 132         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 133
 134 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 135
 136         PR gas/15069
 137         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 138
 139 2013-01-24  Nick Clifton  <nickc@redhat.com>
 140
 141         * v850.h: Add e3v5 support.
 142
 143 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 144
 145         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 146
 147 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 148
 149         * ppc.h (PPC_OPCODE_POWER8): New define.
 150         (PPC_OPCODE_HTM): Likewise.
 151
 152 2013-01-10  Will Newton <will.newton@imgtec.com>
 153
 154         * metag.h: New file.
 155
 156 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 157
 158         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 159         (match_opcode): Rename to cr16_match_opcode.
 160
 161 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 162
 163         * mips.h: Add support for r5900 instructions including lq and sq.
 164
 165 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 166
 167         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 168         (make_instruction,match_opcode): Added function prototypes.
 169         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 170
 171 2012-11-23  Alan Modra  <amodra@gmail.com>
 172
 173         * ppc.h (ppc_parse_cpu): Update prototype.
 174
 175 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 176
 177         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 178         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 179
 180 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 181
 182         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 183
 184 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 185
 186         * ia64.h (ia64_opnd): Add new operand types.
 187
 188 2012-08-21  David S. Miller  <davem@davemloft.net>
 189
 190         * sparc.h (F3F4): New macro.
 191
 192 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 193             Laurent Desnogues  <laurent.desnogues@arm.com>
 194             Jim MacArthur  <jim.macarthur@arm.com>
 195             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 196             Nigel Stephens  <nigel.stephens@arm.com>
 197             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 198             Richard Earnshaw  <rearnsha@arm.com>
 199             Sofiane Naci  <sofiane.naci@arm.com>
 200             Tejas Belagod  <tejas.belagod@arm.com>
 201             Yufeng Zhang  <yufeng.zhang@arm.com>
 202
 203         * aarch64.h: New file.
 204
 205 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 206             Maciej W. Rozycki  <macro@codesourcery.com>
 207
 208         * mips.h (mips_opcode): Add the exclusions field.
 209         (OPCODE_IS_MEMBER): Remove macro.
 210         (cpu_is_member): New inline function.
 211         (opcode_is_member): Likewise.
 212
 213 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 214             Catherine Moore  <clm@codesourcery.com>
 215             Maciej W. Rozycki  <macro@codesourcery.com>
 216
 217         * mips.h: Document microMIPS DSP ASE usage.
 218         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 219         microMIPS DSP ASE support.
 220         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 221         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 222         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 223         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 224         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 225         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 226         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 227
 228 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 229
 230         * mips.h: Fix a typo in description.
 231
 232 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 233
 234         * avr.h: (AVR_ISA_XCH): New define.
 235         (AVR_ISA_XMEGA): Use it.
 236         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 237
 238 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 239
 240         * m68hc11.h: Add XGate definitions.
 241         (struct m68hc11_opcode): Add xg_mask field.
 242
 243 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 244             Maciej W. Rozycki  <macro@codesourcery.com>
 245             Rhonda Wittels  <rhonda@codesourcery.com>
 246
 247         * ppc.h (PPC_OPCODE_VLE): New definition.
 248         (PPC_OP_SA): New macro.
 249         (PPC_OP_SE_VLE): New macro.
 250         (PPC_OP): Use a variable shift amount.
 251         (powerpc_operand): Update comments.
 252         (PPC_OPSHIFT_INV): New macro.
 253         (PPC_OPERAND_CR): Replace with...
 254         (PPC_OPERAND_CR_BIT): ...this and
 255         (PPC_OPERAND_CR_REG): ...this.
 256
 257
 258 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 259
 260         * xgate.h: Header file for XGATE assembler.
 261
 262 2012-04-27  David S. Miller  <davem@davemloft.net>
 263
 264         * sparc.h: Document new arg code' )' for crypto RS3
 265         immediates.
 266
 267         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 268         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 269         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 270         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 271         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 272         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 273         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 274         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 275         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 276         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 277         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 278
 279 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 280
 281         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 282
 283 2012-02-27  Alan Modra  <amodra@gmail.com>
 284
 285         * crx.h (cst4_map): Update declaration.
 286
 287 2012-02-25  Walter Lee  <walt@tilera.com>
 288
 289         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 290         TILEGX_OPC_LD_TLS.
 291         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 292         TILEPRO_OPC_LW_TLS_SN.
 293
 294 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 295
 296         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 297         (XRELEASE_PREFIX_OPCODE): Likewise.
 298
 299 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 300             Adam Nemet  <anemet@caviumnetworks.com>
 301
 302         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 303         (INSN_OCTEON2): New macro.
 304         (CPU_OCTEON2): New macro.
 305         (OPCODE_IS_MEMBER): Add Octeon2.
 306
 307 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 308
 309         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 310         (INSN_OCTEONP): New macro.
 311         (CPU_OCTEONP): New macro.
 312         (OPCODE_IS_MEMBER): Add Octeon+.
 313         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 314
 315 2011-11-01  DJ Delorie  <dj@redhat.com>
 316
 317         * rl78.h: New file.
 318
 319 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 320
 321         * mips.h: Fix a typo in description.
 322
 323 2011-09-21  David S. Miller  <davem@davemloft.net>
 324
 325         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 326         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 327         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 328         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 329
 330 2011-08-09  Chao-ying Fu  <fu@mips.com>
 331             Maciej W. Rozycki  <macro@codesourcery.com>
 332
 333         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 334         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 335         (INSN_ASE_MASK): Add the MCU bit.
 336         (INSN_MCU): New macro.
 337         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 338         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 339
 340 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 341
 342         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 343         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 344         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 345         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 346         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 347         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 348         (INSN2_READ_GPR_MMN): Likewise.
 349         (INSN2_READ_FPR_D): Change the bit used.
 350         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 351         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 352         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 353         (INSN2_COND_BRANCH): Likewise.
 354         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 355         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 356         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 357         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 358         (INSN2_MOD_GPR_MN): Likewise.
 359
 360 2011-08-05  David S. Miller  <davem@davemloft.net>
 361
 362         * sparc.h: Document new format codes '4', '5', and '('.
 363         (OPF_LOW4, RS3): New macros.
 364
 365 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 366
 367         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 368         order of flags documented.
 369
 370 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 371
 372         * mips.h: Clarify the description of microMIPS instruction
 373         manipulation macros.
 374         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 375
 376 2011-07-24  Chao-ying Fu  <fu@mips.com>
 377             Maciej W. Rozycki  <macro@codesourcery.com>
 378
 379         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 380         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 381         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 382         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 383         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 384         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 385         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 386         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 387         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 388         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 389         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 390         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 391         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 392         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 393         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 394         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 395         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 396         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 397         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 398         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 399         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 400         (INSN_WRITE_GPR_S): New macro.
 401         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 402         (INSN2_READ_FPR_D): Likewise.
 403         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 404         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 405         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 406         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 407         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 408         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 409         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 410         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 411         (CPU_MICROMIPS): New macro.
 412         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 413         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 414         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 415         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 416         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 417         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 418         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 419         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 420         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 421         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 422         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 423         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 424         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 425         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 426         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 427         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 428         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 429         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 430         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 431         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 432         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 433         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 434         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 435         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 436         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 437         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 438         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 439         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 440         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 441         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 442         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 443         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 444         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 445         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 446         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 447         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 448         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 449         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 450         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 451         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 452         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 453         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 454         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 455         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 456         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 457         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 458         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 459         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 460         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 461         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 462         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 463         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 464         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 465         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 466         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 467         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 468         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 469         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 470         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 471         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 472         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 473         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 474         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 475         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 476         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 477         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 478         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 479         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 480         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 481         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 482         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 483         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 484         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 485         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 486         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 487         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 488         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 489         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 490         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 491         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 492         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 493         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 494         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 495         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 496         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 497         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 498         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 499         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 500         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 501         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 502         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 503         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 504         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 505         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 506         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 507         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 508         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 509         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 510         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 511         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 512         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 513         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 514         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 515         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 516         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 517         (micromips_opcodes): New declaration.
 518         (bfd_micromips_num_opcodes): Likewise.
 519
 520 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 521
 522         * mips.h (INSN_TRAP): Rename to...
 523         (INSN_NO_DELAY_SLOT): ... this.
 524         (INSN_SYNC): Remove macro.
 525
 526 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 527
 528         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 529         a duplicate of AVR_ISA_SPM.
 530
 531 2011-07-01  Nick Clifton  <nickc@redhat.com>
 532
 533         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 534
 535 2011-06-18  Robin Getz  <robin.getz@analog.com>
 536
 537         * bfin.h (is_macmod_signed): New func
 538
 539 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 540
 541         * bfin.h (is_macmod_pmove): Add missing space before func args.
 542         (is_macmod_hmove): Likewise.
 543
 544 2011-06-13  Walter Lee  <walt@tilera.com>
 545
 546         * tilegx.h: New file.
 547         * tilepro.h: New file.
 548
 549 2011-05-31  Paul Brook  <paul@codesourcery.com>
 550
 551         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 552
 553 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 554
 555         * s390.h: Replace S390_OPERAND_REG_EVEN with
 556         S390_OPERAND_REG_PAIR.
 557
 558 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 559
 560         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 561
 562 2011-04-18  Julian Brown  <julian@codesourcery.com>
 563
 564         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 565
 566 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 567
 568         PR gas/12296
 569         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 570
 571 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 572
 573         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 574         New instruction set flags.
 575         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 576
 577 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 578
 579         * mips.h (M_PREF_AB): New enum value.
 580
 581 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 582
 583         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 584         M_IU): Define.
 585         (is_macmod_pmove, is_macmod_hmove): New functions.
 586
 587 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 588
 589         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 590
 591 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 592
 593         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 594         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 595
 596 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 597
 598         PR gas/11395
 599         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 600         "bb" entries.
 601
 602 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 603
 604         PR gas/11395
 605         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 606
 607 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 608
 609         * mips.h: Update commentary after last commit.
 610
 611 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 612
 613         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 614         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 615         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 616
 617 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 618
 619         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 620
 621 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 622
 623         * mips.h: Fix previous commit.
 624
 625 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 626
 627         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 628         (INSN_LOONGSON_3A): Clear bit 31.
 629
 630 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 631
 632         PR gas/12198
 633         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 634         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 635         (ARM_ARCH_V6M_ONLY): New define.
 636
 637 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 638
 639         * mips.h (INSN_LOONGSON_3A): Defined.
 640         (CPU_LOONGSON_3A): Defined.
 641         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 642
 643 2010-10-09  Matt Rice  <ratmice@gmail.com>
 644
 645         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 646         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 647
 648 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 649
 650         * arm.h (ARM_EXT_VIRT): New define.
 651         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 652         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 653         Extensions.
 654
 655 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 656
 657         * arm.h (ARM_AEXT_ADIV): New define.
 658         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 659
 660 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 661
 662         * arm.h (ARM_EXT_OS): New define.
 663         (ARM_AEXT_V6SM): Likewise.
 664         (ARM_ARCH_V6SM): Likewise.
 665
 666 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 667
 668         * arm.h (ARM_EXT_MP): Add.
 669         (ARM_ARCH_V7A_MP): Likewise.
 670
 671 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 672
 673         * bfin.h: Declare pseudoChr structs/defines.
 674
 675 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 676
 677         * bfin.h: Strip trailing whitespace.
 678
 679 2010-07-29  DJ Delorie  <dj@redhat.com>
 680
 681         * rx.h (RX_Operand_Type): Add TwoReg.
 682         (RX_Opcode_ID): Remove ediv and ediv2.
 683
 684 2010-07-27  DJ Delorie  <dj@redhat.com>
 685
 686         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 687
 688 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 689             Ina Pandit  <ina.pandit@kpitcummins.com>
 690
 691         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 692         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 693         PROCESSOR_V850E2_ALL.
 694         Remove PROCESSOR_V850EA support.
 695         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 696         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 697         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 698         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 699         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 700         V850_OPERAND_PERCENT.
 701         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 702         V850_NOT_R0.
 703         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 704         and V850E_PUSH_POP
 705
 706 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 707
 708         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 709         (MIPS16_INSN_BRANCH): Rename to...
 710         (MIPS16_INSN_COND_BRANCH): ... this.
 711
 712 2010-07-03  Alan Modra  <amodra@gmail.com>
 713
 714         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 715         Renumber other PPC_OPCODE defines.
 716
 717 2010-07-03  Alan Modra  <amodra@gmail.com>
 718
 719         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 720
 721 2010-06-29  Alan Modra  <amodra@gmail.com>
 722
 723         * maxq.h: Delete file.
 724
 725 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 726
 727         * ppc.h (PPC_OPCODE_E500): Define.
 728
 729 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 730
 731         * opcode/mips.h (INSN_MIPS16): Remove.
 732
 733 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 734
 735         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 736
 737 2010-04-15  Nick Clifton  <nickc@redhat.com>
 738
 739         * alpha.h: Update copyright notice to use GPLv3.
 740         * arc.h: Likewise.
 741         * arm.h: Likewise.
 742         * avr.h: Likewise.
 743         * bfin.h: Likewise.
 744         * cgen.h: Likewise.
 745         * convex.h: Likewise.
 746         * cr16.h: Likewise.
 747         * cris.h: Likewise.
 748         * crx.h: Likewise.
 749         * d10v.h: Likewise.
 750         * d30v.h: Likewise.
 751         * dlx.h: Likewise.
 752         * h8300.h: Likewise.
 753         * hppa.h: Likewise.
 754         * i370.h: Likewise.
 755         * i386.h: Likewise.
 756         * i860.h: Likewise.
 757         * i960.h: Likewise.
 758         * ia64.h: Likewise.
 759         * m68hc11.h: Likewise.
 760         * m68k.h: Likewise.
 761         * m88k.h: Likewise.
 762         * maxq.h: Likewise.
 763         * mips.h: Likewise.
 764         * mmix.h: Likewise.
 765         * mn10200.h: Likewise.
 766         * mn10300.h: Likewise.
 767         * msp430.h: Likewise.
 768         * np1.h: Likewise.
 769         * ns32k.h: Likewise.
 770         * or32.h: Likewise.
 771         * pdp11.h: Likewise.
 772         * pj.h: Likewise.
 773         * pn.h: Likewise.
 774         * ppc.h: Likewise.
 775         * pyr.h: Likewise.
 776         * rx.h: Likewise.
 777         * s390.h: Likewise.
 778         * score-datadep.h: Likewise.
 779         * score-inst.h: Likewise.
 780         * sparc.h: Likewise.
 781         * spu-insns.h: Likewise.
 782         * spu.h: Likewise.
 783         * tic30.h: Likewise.
 784         * tic4x.h: Likewise.
 785         * tic54x.h: Likewise.
 786         * tic80.h: Likewise.
 787         * v850.h: Likewise.
 788         * vax.h: Likewise.
 789
 790 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 791
 792         * tic6x-control-registers.h, tic6x-insn-formats.h,
 793         tic6x-opcode-table.h, tic6x.h: New.
 794
 795 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 796
 797         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 798
 799 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 800
 801         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 802
 803 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 804
 805         * ia64.h (ia64_find_opcode): Remove argument name.
 806         (ia64_find_next_opcode): Likewise.
 807         (ia64_dis_opcode): Likewise.
 808         (ia64_free_opcode): Likewise.
 809         (ia64_find_dependency): Likewise.
 810
 811 2009-11-22  Doug Evans  <dje@sebabeach.org>
 812
 813         * cgen.h: Include bfd_stdint.h.
 814         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 815
 816 2009-11-18  Paul Brook  <paul@codesourcery.com>
 817
 818         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 819
 820 2009-11-17  Paul Brook  <paul@codesourcery.com>
 821         Daniel Jacobowitz  <dan@codesourcery.com>
 822
 823         * arm.h (ARM_EXT_V6_DSP): Define.
 824         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 825         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 826
 827 2009-11-04  DJ Delorie  <dj@redhat.com>
 828
 829         * rx.h (rx_decode_opcode) (mvtipl): Add.
 830         (mvtcp, mvfcp, opecp): Remove.
 831
 832 2009-11-02  Paul Brook  <paul@codesourcery.com>
 833
 834         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 835         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 836         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 837         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 838         FPU_ARCH_NEON_VFP_V4): Define.
 839
 840 2009-10-23  Doug Evans  <dje@sebabeach.org>
 841
 842         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 843         * cgen.h: Update.  Improve multi-inclusion macro name.
 844
 845 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 846
 847         * ppc.h (PPC_OPCODE_476): Define.
 848
 849 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 850
 851         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 852
 853 2009-09-29  DJ Delorie  <dj@redhat.com>
 854
 855         * rx.h: New file.
 856
 857 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 858
 859         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 860
 861 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 862
 863         * ppc.h (PPC_OPCODE_PPCA2): New.
 864
 865 2009-09-05  Martin Thuresson  <martin@mtme.org>
 866
 867         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 868
 869 2009-08-29  Martin Thuresson  <martin@mtme.org>
 870
 871         * tic30.h (template): Rename type template to
 872         insn_template. Updated code to use new name.
 873         * tic54x.h (template): Rename type template to
 874         insn_template.
 875
 876 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 877
 878         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 879
 880 2009-06-11  Anthony Green  <green@moxielogic.com>
 881
 882         * moxie.h (MOXIE_F3_PCREL): Define.
 883         (moxie_form3_opc_info): Grow.
 884
 885 2009-06-06  Anthony Green  <green@moxielogic.com>
 886
 887         * moxie.h (MOXIE_F1_M): Define.
 888
 889 2009-04-15  Anthony Green  <green@moxielogic.com>
 890
 891         * moxie.h: Created.
 892
 893 2009-04-06  DJ Delorie  <dj@redhat.com>
 894
 895         * h8300.h: Add relaxation attributes to MOVA opcodes.
 896
 897 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 898
 899         * ppc.h (ppc_parse_cpu): Declare.
 900
 901 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 902
 903         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 904         and _IMM11 for mbitclr and mbitset.
 905         * score-datadep.h: Update dependency information.
 906
 907 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 908
 909         * ppc.h (PPC_OPCODE_POWER7): New.
 910
 911 2009-02-06  Doug Evans  <dje@google.com>
 912
 913         * i386.h: Add comment regarding sse* insns and prefixes.
 914
 915 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 916
 917         * mips.h (INSN_XLR): Define.
 918         (INSN_CHIP_MASK): Update.
 919         (CPU_XLR): Define.
 920         (OPCODE_IS_MEMBER): Update.
 921         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 922
 923 2009-01-28  Doug Evans  <dje@google.com>
 924
 925         * opcode/i386.h: Add multiple inclusion protection.
 926         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 927         (EDI_REG_NUM): New macros.
 928         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 929         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 930         (REX_PREFIX_P): New macro.
 931
 932 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 933
 934         * ppc.h (struct powerpc_opcode): New field "deprecated".
 935         (PPC_OPCODE_NOPOWER4): Delete.
 936
 937 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 938
 939         * mips.h: Define CPU_R14000, CPU_R16000.
 940         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 941
 942 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 943
 944         * arm.h (FPU_NEON_FP16): New.
 945         (FPU_ARCH_NEON_FP16): New.
 946
 947 2008-11-06  Chao-ying Fu  <fu@mips.com>
 948
 949         * mips.h: Doucument '1' for 5-bit sync type.
 950
 951 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 952
 953         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 954         IA64_RS_CR.
 955
 956 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 957
 958         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 959
 960 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 961
 962         * ppc.h (PPC_OPCODE_405): Define.
 963         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 964
 965 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 966
 967         * ppc.h (ppc_cpu_t): New typedef.
 968         (struct powerpc_opcode <flags>): Use it.
 969         (struct powerpc_operand <insert, extract>): Likewise.
 970         (struct powerpc_macro <flags>): Likewise.
 971
 972 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 973
 974         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 975         Update comment before MIPS16 field descriptors to mention MIPS16.
 976         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 977         BBIT.
 978         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 979         New bit masks and shift counts for cins and exts.
 980
 981         * mips.h: Document new field descriptors +Q.
 982         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 983
 984 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 985
 986         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 987         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 988
 989 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 990
 991         * ppc.h: (PPC_OPCODE_E500MC): New.
 992
 993 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 994
 995         * i386.h (MAX_OPERANDS): Set to 5.
 996         (MAX_MNEM_SIZE): Changed to 20.
 997
 998 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 999
1000         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1001
1002 2008-03-09  Paul Brook  <paul@codesourcery.com>
1003
1004         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1005
1006 2008-03-04  Paul Brook  <paul@codesourcery.com>
1007
1008         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1009         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1010         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1011
1012 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1013             Nick Clifton  <nickc@redhat.com>
1014
1015         PR 3134
1016         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1017         with a 32-bit displacement but without the top bit of the 4th byte
1018         set.
1019
1020 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1021
1022         * cr16.h (cr16_num_optab): Declared.
1023
1024 2008-02-14  Hakan Ardo  <hakan@debian.org>
1025
1026         PR gas/2626
1027         * avr.h (AVR_ISA_2xxe): Define.
1028
1029 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1030
1031         * mips.h: Update copyright.
1032         (INSN_CHIP_MASK): New macro.
1033         (INSN_OCTEON): New macro.
1034         (CPU_OCTEON): New macro.
1035         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1036
1037 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1038
1039         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1040
1041 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1042
1043         * avr.h (AVR_ISA_USB162): Add new opcode set.
1044         (AVR_ISA_AVR3): Likewise.
1045
1046 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1047
1048         * mips.h (INSN_LOONGSON_2E): New.
1049         (INSN_LOONGSON_2F): New.
1050         (CPU_LOONGSON_2E): New.
1051         (CPU_LOONGSON_2F): New.
1052         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1053
1054 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1055
1056         * mips.h (INSN_ISA*): Redefine certain values as an
1057         enumeration.  Update comments.
1058         (mips_isa_table): New.
1059         (ISA_MIPS*): Redefine to match enumeration.
1060         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1061         values.
1062
1063 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1064
1065         * ppc.h (PPC_OPCODE_PPCPS): New.
1066
1067 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1068
1069         * m68k.h: Document j K & E.
1070
1071 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1072
1073         * cr16.h: New file for CR16 target.
1074
1075 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1076
1077         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1078
1079 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1080
1081         * m68k.h (mcfisa_c): New.
1082         (mcfusp, mcf_mask): Adjust.
1083
1084 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1085
1086         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1087         (num_powerpc_operands): Declare.
1088         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1089         (PPC_OPERAND_PLUS1): Define.
1090
1091 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1092
1093         * i386.h (REX_MODE64): Renamed to ...
1094         (REX_W): This.
1095         (REX_EXTX): Renamed to ...
1096         (REX_R): This.
1097         (REX_EXTY): Renamed to ...
1098         (REX_X): This.
1099         (REX_EXTZ): Renamed to ...
1100         (REX_B): This.
1101
1102 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1103
1104         * i386.h: Add entries from config/tc-i386.h and move tables
1105         to opcodes/i386-opc.h.
1106
1107 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1108
1109         * i386.h (FloatDR): Removed.
1110         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1111
1112 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1113
1114         * spu-insns.h: Add soma double-float insns.
1115
1116 2007-02-20  Thiemo Seufer  <ths@mips.com>
1117             Chao-Ying Fu  <fu@mips.com>
1118
1119         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1120         (INSN_DSPR2): Add flag for DSP R2 instructions.
1121         (M_BALIGN): New macro.
1122
1123 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1124
1125         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1126         and Seg3ShortFrom with Shortform.
1127
1128 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1129
1130         PR gas/4027
1131         * i386.h (i386_optab): Put the real "test" before the pseudo
1132         one.
1133
1134 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1135
1136         * m68k.h (m68010up): OR fido_a.
1137
1138 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1139
1140         * m68k.h (fido_a): New.
1141
1142 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1143
1144         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1145         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1146         values.
1147
1148 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1149
1150         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1151
1152 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1153
1154         * score-inst.h (enum score_insn_type): Add Insn_internal.
1155
1156 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1157             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1158             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1159             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1160             Alan Modra  <amodra@bigpond.net.au>
1161
1162         * spu-insns.h: New file.
1163         * spu.h: New file.
1164
1165 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1166
1167         * ppc.h (PPC_OPCODE_CELL): Define.
1168
1169 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1170
1171         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1172         in amdfam10 architecture.
1173
1174 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1175
1176         * i386.h: Replace CpuMNI with CpuSSSE3.
1177
1178 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1179             Joseph Myers  <joseph@codesourcery.com>
1180             Ian Lance Taylor  <ian@wasabisystems.com>
1181             Ben Elliston  <bje@wasabisystems.com>
1182
1183         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1184
1185 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1186
1187         * score-datadep.h: New file.
1188         * score-inst.h: New file.
1189
1190 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1191
1192         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1193         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1194         movdq2q and movq2dq.
1195
1196 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1197            Michael Meissner             <michael.meissner@amd.com>
1198
1199         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1200
1201 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1202
1203         * i386.h (i386_optab): Add "nop" with memory reference.
1204
1205 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1206
1207         * i386.h (i386_optab): Update comment for 64bit NOP.
1208
1209 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1210             Anton Blanchard  <anton@samba.org>
1211
1212         * ppc.h (PPC_OPCODE_POWER6): Define.
1213         Adjust whitespace.
1214
1215 2006-06-05  Thiemo Seufer  <ths@mips.com>
1216
1217         * mips.h: Improve description of MT flags.
1218
1219 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1220
1221         * m68k.h (mcf_mask): Define.
1222
1223 2006-05-05  Thiemo Seufer  <ths@mips.com>
1224             David Ung  <davidu@mips.com>
1225
1226         * mips.h (enum): Add macro M_CACHE_AB.
1227
1228 2006-05-04  Thiemo Seufer  <ths@mips.com>
1229             Nigel Stephens  <nigel@mips.com>
1230             David Ung  <davidu@mips.com>
1231
1232         * mips.h: Add INSN_SMARTMIPS define.
1233
1234 2006-04-30  Thiemo Seufer  <ths@mips.com>
1235             David Ung  <davidu@mips.com>
1236
1237         * mips.h: Defines udi bits and masks.  Add description of
1238         characters which may appear in the args field of udi
1239         instructions.
1240
1241 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1242
1243         * mips.h: Improve comments describing the bitfield instruction
1244         fields.
1245
1246 2006-04-26  Julian Brown  <julian@codesourcery.com>
1247
1248         * arm.h (FPU_VFP_EXT_V3): Define constant.
1249         (FPU_NEON_EXT_V1): Likewise.
1250         (FPU_VFP_HARD): Update.
1251         (FPU_VFP_V3): Define macro.
1252         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1253
1254 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1255
1256         * avr.h (AVR_ISA_PWMx): New.
1257
1258 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1259
1260         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1261         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1262         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1263         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1264         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1265
1266 2006-03-10  Paul Brook  <paul@codesourcery.com>
1267
1268         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1269
1270 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1271
1272         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1273         first.  Correct mask of bb "B" opcode.
1274
1275 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1276
1277         * i386.h (i386_optab): Support Intel Merom New Instructions.
1278
1279 2006-02-24  Paul Brook  <paul@codesourcery.com>
1280
1281         * arm.h: Add V7 feature bits.
1282
1283 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1284
1285         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1286
1287 2006-01-31  Paul Brook  <paul@codesourcery.com>
1288         Richard Earnshaw <rearnsha@arm.com>
1289
1290         * arm.h: Use ARM_CPU_FEATURE.
1291         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1292         (arm_feature_set): Change to a structure.
1293         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1294         ARM_FEATURE): New macros.
1295
1296 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1297
1298         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1299         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1300         (ADD_PC_INCR_OPCODE): Don't define.
1301
1302 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1303
1304         PR gas/1874
1305         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1306
1307 2005-11-14  David Ung  <davidu@mips.com>
1308
1309         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1310         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1311         save/restore encoding of the args field.
1312
1313 2005-10-28  Dave Brolley  <brolley@redhat.com>
1314
1315         Contribute the following changes:
1316         2005-02-16  Dave Brolley  <brolley@redhat.com>
1317
1318         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1319         cgen_isa_mask_* to cgen_bitset_*.
1320         * cgen.h: Likewise.
1321
1322         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1323
1324         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1325         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1326         (CGEN_CPU_TABLE): Make isas a ponter.
1327
1328         2003-09-29  Dave Brolley  <brolley@redhat.com>
1329
1330         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1331         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1332         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1333
1334         2002-12-13  Dave Brolley  <brolley@redhat.com>
1335
1336         * cgen.h (symcat.h): #include it.
1337         (cgen-bitset.h): #include it.
1338         (CGEN_ATTR_VALUE_TYPE): Now a union.
1339         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1340         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1341         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1342         * cgen-bitset.h: New file.
1343
1344 2005-09-30  Catherine Moore  <clm@cm00re.com>
1345
1346         * bfin.h: New file.
1347
1348 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1349
1350         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1351         indirect operands.
1352
1353 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1354
1355         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1356         Add FLAG_STRICT to pa10 ftest opcode.
1357
1358 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1359
1360         * hppa.h (pa_opcodes): Remove lha entries.
1361
1362 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1363
1364         * hppa.h (FLAG_STRICT): Revise comment.
1365         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1366         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1367         entries for "fdc".
1368
1369 2005-09-30  Catherine Moore  <clm@cm00re.com>
1370
1371         * bfin.h: New file.
1372
1373 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1374
1375         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1376
1377 2005-09-06  Chao-ying Fu  <fu@mips.com>
1378
1379         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1380         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1381         define.
1382         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1383         (INSN_ASE_MASK): Update to include INSN_MT.
1384         (INSN_MT): New define for MT ASE.
1385
1386 2005-08-25  Chao-ying Fu  <fu@mips.com>
1387
1388         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1389         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1390         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1391         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1392         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1393         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1394         instructions.
1395         (INSN_DSP): New define for DSP ASE.
1396
1397 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1398
1399         * a29k.h: Delete.
1400
1401 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1402
1403         * ppc.h (PPC_OPCODE_E300): Define.
1404
1405 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1406
1407         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1408
1409 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1410
1411         PR gas/336
1412         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1413         and pitlb.
1414
1415 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1416
1417         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1418         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1419         Add movq-s as 64-bit variants of movd-s.
1420
1421 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1422
1423         * hppa.h: Fix punctuation in comment.
1424
1425         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1426         implicit space-register addressing.  Set space-register bits on opcodes
1427         using implicit space-register addressing.  Add various missing pa20
1428         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1429         space-register addressing.  Use "fE" instead of "fe" in various
1430         fstw opcodes.
1431
1432 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1433
1434         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1435
1436 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1437
1438         * i386.h (i386_optab): Support Intel VMX Instructions.
1439
1440 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1441
1442         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1443
1444 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1445
1446         * i386.h (i386_optab): Add new insns.
1447
1448 2005-07-01  Nick Clifton  <nickc@redhat.com>
1449
1450         * sparc.h: Add typedefs to structure declarations.
1451
1452 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1453
1454         PR 1013
1455         * i386.h (i386_optab): Update comments for 64bit addressing on
1456         mov. Allow 64bit addressing for mov and movq.
1457
1458 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1459
1460         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1461         respectively, in various floating-point load and store patterns.
1462
1463 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1464
1465         * hppa.h (FLAG_STRICT): Correct comment.
1466         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1467         PA 2.0 mneumonics when equivalent.  Entries with cache control
1468         completers now require PA 1.1.  Adjust whitespace.
1469
1470 2005-05-19  Anton Blanchard  <anton@samba.org>
1471
1472         * ppc.h (PPC_OPCODE_POWER5): Define.
1473
1474 2005-05-10  Nick Clifton  <nickc@redhat.com>
1475
1476         * Update the address and phone number of the FSF organization in
1477         the GPL notices in the following files:
1478         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1479         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1480         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1481         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1482         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1483         tic54x.h, tic80.h, v850.h, vax.h
1484
1485 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1486
1487         * i386.h (i386_optab): Add ht and hnt.
1488
1489 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1490
1491         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1492         Add xcrypt-ctr.  Provide aliases without hyphens.
1493
1494 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1495
1496         Moved from ../ChangeLog
1497
1498         2005-04-12  Paul Brook  <paul@codesourcery.com>
1499         * m88k.h: Rename psr macros to avoid conflicts.
1500
1501         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1502         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1503         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1504         and ARM_ARCH_V6ZKT2.
1505
1506         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1507         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1508         Remove redundant instruction types.
1509         (struct argument): X_op - new field.
1510         (struct cst4_entry): Remove.
1511         (no_op_insn): Declare.
1512
1513         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1514         * crx.h (enum argtype): Rename types, remove unused types.
1515
1516         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1517         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1518         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1519         (enum operand_type): Rearrange operands, edit comments.
1520         replace us<N> with ui<N> for unsigned immediate.
1521         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1522         displacements (respectively).
1523         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1524         (instruction type): Add NO_TYPE_INS.
1525         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1526         (operand_entry): New field - 'flags'.
1527         (operand flags): New.
1528
1529         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1530         * crx.h (operand_type): Remove redundant types i3, i4,
1531         i5, i8, i12.
1532         Add new unsigned immediate types us3, us4, us5, us16.
1533
1534 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1535
1536         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1537         adjust them accordingly.
1538
1539 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1540
1541         * i386.h (i386_optab): Add rdtscp.
1542
1543 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1544
1545         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1546         between memory and segment register. Allow movq for moving between
1547         general-purpose register and segment register.
1548
1549 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1550
1551         PR gas/707
1552         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1553         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1554         fnstsw.
1555
1556 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1557
1558         * m68k.h (m68008, m68ec030, m68882): Remove.
1559         (m68k_mask): New.
1560         (cpu_m68k, cpu_cf): New.
1561         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1562         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1563
1564 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1565
1566         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1567         * cgen.h (enum cgen_parse_operand_type): Add
1568         CGEN_PARSE_OPERAND_SYMBOLIC.
1569
1570 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1571
1572         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1573         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1574         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1575
1576 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1577
1578         * mips.h (struct mips_opcode): Add new pinfo2 member.
1579         (INSN_ALIAS): New define for opcode table entries that are
1580         specific instances of another entry, such as 'move' for an 'or'
1581         with a zero operand.
1582         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1583         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1584
1585 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1586
1587         * mips.h (CPU_RM9000): Define.
1588         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1589
1590 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1591
1592         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1593         to/from test registers are illegal in 64-bit mode. Add missing
1594         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1595         (previously one had to explicitly encode a rex64 prefix). Re-enable
1596         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1597         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1598
1599 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1600
1601         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1602         available only with SSE2. Change the MMX additions introduced by SSE
1603         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1604         instructions by their now designated identifier (since combining i686
1605         and 3DNow! does not really imply 3DNow!A).
1606
1607 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1608
1609         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1610         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1611
1612 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1613             Vineet Sharma      <vineets@noida.hcltech.com>
1614
1615         * maxq.h: New file: Disassembly information for the maxq port.
1616
1617 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1618
1619         * i386.h (i386_optab): Put back "movzb".
1620
1621 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1622
1623         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1624         comments.  Remove member cris_ver_sim.  Add members
1625         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1626         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1627         (struct cris_support_reg, struct cris_cond15): New types.
1628         (cris_conds15): Declare.
1629         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1630         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1631         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1632         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1633         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1634         SIZE_FIELD_UNSIGNED.
1635
1636 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1637
1638         * i386.h (sldx_Suf): Remove.
1639         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1640         (q_FP): Define, implying no REX64.
1641         (x_FP, sl_FP): Imply FloatMF.
1642         (i386_optab): Split reg and mem forms of moving from segment registers
1643         so that the memory forms can ignore the 16-/32-bit operand size
1644         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1645         all non-floating-point instructions. Unite 32- and 64-bit forms of
1646         movsx, movzx, and movd. Adjust floating point operations for the above
1647         changes to the *FP macros. Add DefaultSize to floating point control
1648         insns operating on larger memory ranges. Remove left over comments
1649         hinting at certain insns being Intel-syntax ones where the ones
1650         actually meant are already gone.
1651
1652 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1653
1654         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1655         instruction type.
1656
1657 2004-09-30  Paul Brook  <paul@codesourcery.com>
1658
1659         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1660         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1661
1662 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1663
1664         * avr.h: Add support for
1665         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1666
1667 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1668
1669         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1670
1671 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1672
1673         * msp430.h (msp430_opc): Add new instructions.
1674         (msp430_rcodes): Declare new instructions.
1675         (msp430_hcodes): Likewise..
1676
1677 2004-08-13  Nick Clifton  <nickc@redhat.com>
1678
1679         PR/301
1680         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1681         processors.
1682
1683 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1684
1685         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1686
1687 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1688
1689         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1690
1691 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1692
1693         * i386.h: Adjust instruction descriptions to better match the
1694         specification.
1695
1696 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1697
1698         * arm.h: Remove all old content.  Replace with architecture defines
1699         from gas/config/tc-arm.c.
1700
1701 2004-07-09  Andreas Schwab  <schwab@suse.de>
1702
1703         * m68k.h: Fix comment.
1704
1705 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1706
1707         * crx.h: New file.
1708
1709 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1710
1711         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1712
1713 2004-05-24  Peter Barada  <peter@the-baradas.com>
1714
1715         * m68k.h: Add 'size' to m68k_opcode.
1716
1717 2004-05-05  Peter Barada  <peter@the-baradas.com>
1718
1719         * m68k.h: Switch from ColdFire chip name to core variant.
1720
1721 2004-04-22  Peter Barada  <peter@the-baradas.com>
1722
1723         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1724         descriptions for new EMAC cases.
1725         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1726         handle Motorola MAC syntax.
1727         Allow disassembly of ColdFire V4e object files.
1728
1729 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1730
1731         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1732
1733 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1734
1735         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1736
1737 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1738
1739         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1740
1741 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1742
1743         * i386.h (i386_optab): Added xstore/xcrypt insns.
1744
1745 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1746
1747         * h8300.h (32bit ldc/stc): Add relaxing support.
1748
1749 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1750
1751         * h8300.h (BITOP): Pass MEMRELAX flag.
1752
1753 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1754
1755         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1756         except for the H8S.
1757
1758 For older changes see ChangeLog-9103
1759 \f
1760 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1761
1762 Copying and distribution of this file, with or without modification,
1763 are permitted in any medium without royalty provided the copyright
1764 notice and this notice are preserved.
1765
1766 Local Variables:
1767 mode: change-log
1768 left-margin: 8
1769 fill-column: 74
1770 version-control: never
1771 End: