include/opcode/ChangeLog

   1 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386.h (i386_optab): Don't allow the `l' suffix for moving
   4         moving between memory and segment register. Allow movq for
   5         moving between general-purpose register and segment register.
   6
   7 2005-02-09  Jan Beulich  <jbeulich@novell.com>
   8
   9         PR gas/707
  10         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
  11         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
  12         fnstsw.
  13
  14 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  15
  16         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  17         * cgen.h (enum cgen_parse_operand_type): Add
  18         CGEN_PARSE_OPERAND_SYMBOLIC.
  19
  20 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  21
  22         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
  23         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  24         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  25
  26 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  27
  28         * mips.h (struct mips_opcode): Add new pinfo2 member.
  29         (INSN_ALIAS): New define for opcode table entries that are
  30         specific instances of another entry, such as 'move' for an 'or'
  31         with a zero operand.
  32         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
  33         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
  34
  35 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
  36
  37         * mips.h (CPU_RM9000): Define.
  38         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
  39
  40 2004-11-25 Jan Beulich  <jbeulich@novell.com>
  41
  42         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
  43         to/from test registers are illegal in 64-bit mode. Add missing
  44         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
  45         (previously one had to explicitly encode a rex64 prefix). Re-enable
  46         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
  47         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
  48
  49 2004-11-23 Jan Beulich  <jbeulich@novell.com>
  50
  51         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
  52         available only with SSE2. Change the MMX additions introduced by SSE
  53         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
  54         instructions by their now designated identifier (since combining i686
  55         and 3DNow! does not really imply 3DNow!A).
  56
  57 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  58
  59         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
  60         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
  61
  62 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  63             Vineet Sharma      <vineets@noida.hcltech.com>
  64
  65         * maxq.h: New file: Disassembly information for the maxq port.
  66
  67 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
  68
  69         * i386.h (i386_optab): Put back "movzb".
  70
  71 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  72
  73         * cris.h (enum cris_insn_version_usage): Tweak formatting and
  74         comments.  Remove member cris_ver_sim.  Add members
  75         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
  76         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
  77         (struct cris_support_reg, struct cris_cond15): New types.
  78         (cris_conds15): Declare.
  79         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
  80         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
  81         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
  82         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
  83         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
  84         SIZE_FIELD_UNSIGNED.
  85
  86 2004-11-04 Jan Beulich  <jbeulich@novell.com>
  87
  88         * i386.h (sldx_Suf): Remove.
  89         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
  90         (q_FP): Define, implying no REX64.
  91         (x_FP, sl_FP): Imply FloatMF.
  92         (i386_optab): Split reg and mem forms of moving from segment registers
  93         so that the memory forms can ignore the 16-/32-bit operand size
  94         distinction. Adjust a few others for Intel mode. Remove *FP uses from
  95         all non-floating-point instructions. Unite 32- and 64-bit forms of
  96         movsx, movzx, and movd. Adjust floating point operations for the above
  97         changes to the *FP macros. Add DefaultSize to floating point control
  98         insns operating on larger memory ranges. Remove left over comments
  99         hinting at certain insns being Intel-syntax ones where the ones
 100         actually meant are already gone.
 101
 102 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 103
 104         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 105         instruction type.
 106
 107 2004-09-30  Paul Brook  <paul@codesourcery.com>
 108
 109         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 110         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 111
 112 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 113
 114         * avr.h: Add support for
 115         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 116
 117 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 118
 119         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 120
 121 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 122
 123         * msp430.h (msp430_opc): Add new instructions.
 124         (msp430_rcodes): Declare new instructions.
 125         (msp430_hcodes): Likewise..
 126
 127 2004-08-13  Nick Clifton  <nickc@redhat.com>
 128
 129         PR/301
 130         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 131         processors.
 132
 133 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 134
 135         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 136
 137 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 140
 141 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 142
 143         * i386.h: Adjust instruction descriptions to better match the
 144         specification.
 145
 146 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 147
 148         * arm.h: Remove all old content.  Replace with architecture defines
 149         from gas/config/tc-arm.c.
 150
 151 2004-07-09  Andreas Schwab  <schwab@suse.de>
 152
 153         * m68k.h: Fix comment.
 154
 155 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 156
 157         * crx.h: New file.
 158
 159 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 160
 161         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 162
 163 2004-05-24  Peter Barada  <peter@the-baradas.com>
 164
 165         * m68k.h: Add 'size' to m68k_opcode.
 166
 167 2004-05-05  Peter Barada  <peter@the-baradas.com>
 168
 169         * m68k.h: Switch from ColdFire chip name to core variant.
 170
 171 2004-04-22  Peter Barada  <peter@the-baradas.com>
 172
 173         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 174         descriptions for new EMAC cases.
 175         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 176         handle Motorola MAC syntax.
 177         Allow disassembly of ColdFire V4e object files.
 178
 179 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 180
 181         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 182
 183 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 184
 185         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 186
 187 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 188
 189         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 190
 191 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 192
 193         * i386.h (i386_optab): Added xstore/xcrypt insns.
 194
 195 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 196
 197         * h8300.h (32bit ldc/stc): Add relaxing support.
 198
 199 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 200
 201         * h8300.h (BITOP): Pass MEMRELAX flag.
 202
 203 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 204
 205         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 206         except for the H8S.
 207
 208 For older changes see ChangeLog-9103
 209 \f
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